Toshiba GR-200-5 Instruction Manual

Also see for GR 200 Series: Instruction manual Instruction manual Instruction manual Instruction manual Instruction manual

6F2T0207 (0.01)GRE200 (5,6)- 658 -(ii) Programmable binary input circuitsBinary input circuits (BI) can have a pick-up threshold for the input signal. It can be set withsetting [BITH*]. If chattering signals caused by bouncing contacts are coming, circuit filter canremove the chattering. The filter performance is set with setting [CMP_NUM]. Each binary BIis constructed with retard and invert logics, so the user can program the circuit with settings[On Delay Timer], [Off Delay Timer], [INVERSE-SW]; then set On for the respective setting[BI*_CPL].Figure 5.6-9 shows binary input circuits, which consists of potential divider, filter, On/Off delaytimer, and inversion logics.80010011111BI1[INVERSE-SW]≥1&[BI1-CPL] OffOn&BI2BI3BInFilter t 00.000-300.000s[On Delay Timer]0 t0.000-300.000sNormalInverse&&≥1[INVERSE-SW]≥1&[BI2-CPL]&t 00.000-300.000s0 t0.000-300.000sNormalInverse& ≥1[INVERSE-SW]≥1&[BI3-CPL]&t 00.000-300.000s0 t0.000-300.000sNormalInverse& ≥1[INVERSE-SW]≥18**********&[BIn-CPL]&t 00.000-300.000s0 t0.000-300.000sNormalInverse& ≥1BI1581010111118201021110800100111081010111108201021110800100117281010111728201021172BI1-NCBI2-NCBI3-NCBIn-NCBI1BI2BI15BI3BI1-CPLBI2-CPLBI3-CPLBIn-CPL8**********To internalFrom external1 &1 &1 &R[BITH1]RRRLevel_1Level_2Level_3Level_4[Off Delay Timer]OffOnOffOnOffOnR[BITH2]RRLevel_1Level_2Level_3(–)(+)(–)(+)(+)[On Delay Timer] [Off Delay Timer][On Delay Timer] [Off Delay Timer][On Delay Timer] [Off Delay Timer](–)(–)(+)BI BIFigure 5.6-9 Programmable logics of binary input circuits