Toshiba GR-200-5 Instruction Manual

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6F2T0207 (0.01)GRE200 (5,6)- 1013 -Figure 12.6-6 CPL setting (Sample)Note: Setting items “On Delay timer and others” are displayed when the user sets[BI*_CPL] On.(iii) Binary outputAll binary output circuits (BOs) are also user-configurable; the user can configure timers andswitches using CPL settings. (For more information of CPL, see ChapterTechnical description:Binary IO module: Binary output circuit →p. 663)Selection of binary output circuit: Figure 12.6-7 illustrates the selection of abinary output circuit on a BIO module. Move the cursor by pressing ▲ and▼. Press ► to go to the next level in the hierarchy.Figure 12.6-7 Selection of slot and binary output circuit (Sample)CPL Setting: Figure 12.6-8 illustrates the setting of a BO circuit (BO1). Whensetting [BI1_CPL]=On, the BO1 CPL logic is applicable. Assigned signals,timers and switches should be set using this menu. Note that detailed settingitems are shown when On is keyed into setting [BI*_CPL].BI110:48 1/4BI1_CPL +OffOn Delay Timer +0.000 sOff Delay Timer +0.000 sInverse-SW +NormalBinary Output10:48 2/3Slot#1 >_Slot#2 >Slot#3 > [►]Slot#210:48 1/6_BO1 >BO2 >BO3 >BO4 >BO5 >BO6 >