S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS4-114.1.8 CMP2CON — COMPARATOR1 CONTROL REGISTER: ECH, BANK0Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESET Value 0 0 0 0 0 0 1 0Read/Write R/W R/W R/W R/W R/W R/W R R/WComparator 2 Reference Level Selection Bit0 0 0 0.45VDD0 0 1 0.50VDD0 1 0 0.55VDD0 1 1 0.60VDD1 0 0 0.65VDD1 0 1 0.70VDD1 1 0 0.75VDD.7–.51 1 1 0.80VDDComparator2 Output Polarity Select Bit0 Does not invert CMP2 output..41 Inverts CMP2 output.Comparator2 Enable Bit0 Disables CMP1..31 Enables CMP1.Comparator2 Interrupt Enable Bit0 Disables CMP1 interrupt..21 Enables CMP1 interrupt.Comparator2 Status Bit0 CMP2_N > CMP2_P.11 CMP2_N < CMP2_PComparator2 Pending Bit0 No interrupt is pending (clears pending bit when write)..01 CMP2 interrupt is pending.NOTE:1. Polarity selection bit (CMP2CON.4) will not affect the interrupt generation logic.2. Refer to “Programming Tip” in Chapter 14 for proper configuration sequence.
