Contents - Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- OVERVIEW OF S3F84B8 MICROCONTROLLER
- Key Features of S3F84B8
- Block Diagram of S3F84B8
- Pin Assignments
- Pin Descriptions
- Table 1-2 Pin Descriptions used to Read/Write the Flash ROM
- Pin Circuits
- Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)
- ADDRESS SPACES
- Internal Program Memory (ROM)
- Smart Option
- Register Architecture
- Figure 2-3 Internal Register File Organization in S3F84B8
- Register Page Pointer (PP)
- Register Set 1
- Prime Register Space
- Working Registers
- Using The Register Points (RP)
- Figure 2-8 Non-Contiguous 16 Byte Working Register Block
- Register Addressing
- Common Working Register Area (C0H–CFH)
- Bit Working Register Addressing
- Figure 2-13 4-Bit Working Register Addressing Example
- Figure 2-15 8-Bit Working Register Addressing Example
- System and User Stack
- ADDRESSING MODES
- Register (R) Addressing Mode
- Indirect Register (IR) Addressing Mode
- Indirect Register (IR) Addressing Mode (Continued)
- Indirect Register (IR) Addressing Mode (Concluded)
- Indexed (X) Addressing Mode
- Indexed (X) Addressing Mode (Continued)
- Indexed (X) Addressing Mode (Concluded)
- Direct Address (DA) Mode
- Direct Address (DA) Mode (Continued)
- Indirect Address (IA) Mode
- Relative Address (RA) Mode
- Immediate Mode (IM)
- CONTROL REGISTERS
- ADCON — A/D Converter Control Register: FAH, BANK0
- AMTDATA — Anti-mis-trigger Data Register: F6H, BANK0
- BUZCON — BUZ Control Register: F7H, BANK0
- CLKCON — Clock Control Register: D4H, BANK0
- CMP0CON — Comparator0 Control Register: EAH, BANK0
- CMP1CON — Comparator1 Control Register: EBH, BANK0
- CMP2CON — Comparator1 Control Register: ECH, BANK0
- CMP3CON — Comparator1 Control Register: EDH, BANK0
- CMPINT — Comparator Interrupt Mode Control Register: EEH, BANK0
- FLAGS — System Flags Register: D5H, BANK0
- FMCON — Flash Memory Control Register: F5H, BANK1
- FMSECL — Flash Memory Sector Address Register (Low Byte): F8H, BANK1
- IMR — Interrupt Mask Register: DDH, BANK0
- IPH — Instruction Pointer (High Byte): DAH, BANK0
- IPR — Interrupt Priority Register: FFH, BANK0
- IRQ — Interrupt Request Register: DCH, BANK0
- OPACON — OP AMP Control Register: E0H, BANK1
- P0CONH — Port 0 Control Register (High Byte): E4H, Bank0
- P0CONL — Port 0 Control Register (Low Byte): E5H, BANK0
- P0INT — Port 0 Interrupt Control Register: E3H, BANK0
- P0PND — Port 0 Interrupt Pending Register: E6H, BANK0
- P1CON — Port 1 Control Register: E7H, BANK0
- P2CONH — Port 2 Control Register (High Byte): E8H, BANK0
- P2CONL — Port 2 Control Register (Low Byte): E9H, BANK0
- PWMCON — PWM Control Register: EFH, BANK0
- PWMCCON — PWM CMP Control Register: F0H, BANK0
- PWMDL — Comparator0 Output Delay Register: F5H, Bank0
- RESETID — Reset Source Indicating Register: F2H, BANK1
- RP0 — Register Pointer 0: D6H, BANK0
- SPL — Stack Pointer: D9H, BANK0
- SYM — System Mode Register: DEH, BANK0
- TACON — Timer A Control Register: E1H, BANK1
- TAPS — TA Pre-scalar Register: E2H, BANK1
- TCCON — Timer C Control Register: E5H, BANK1
- TCPS — TC Pre-scalar Register: E6H, BANK1
- TDCON — Timer D Control Register: E9H, BANK1
- TDPS — TD Pre-scalar Register: EAH, BANK1
- INTERRUPT STRUCTURE
- Interrupt Types
- S3F84B8 Interrupt Structure
- Interrupt Vector Addresses
- System-Level Interrupt Control Registers
- Interrupt Processing Control Points
- Peripheral Interrupt Control Registers
- System Mode Register (SYM)
- Interrupt Mask Register (IMR)
- Interrupt Priority Register (IPR)
- Interrupt Request Register (IRQ)
- Interrupt Pending Function Types
- Interrupt Source Polling Sequence
- Generating Interrupt Vector Addresses
- Instruction Pointer (IP)
- Procedure for Initiating Fast Interrupts
- INSTRUCTION SET
- Flags Register (FLAGS)
- Flag Descriptions
- Instruction Set Notation
- Table 6-4 Instruction Notation Conventions
- Table 6-5 Opcode Quick Reference
- Condition Codes
- Instruction Descriptions
- ADC — Add with Carry
- ADD — Add
- AND — Logical AND
- BAND — Bit AND
- BCP — Bit Compare
- BITC — Bit Complement
- BITR — Bit Reset
- BITS — Bit Set
- BOR — Bit OR
- BTJRF — Bit Test, Jump Relative on False
- BTJRT — Bit Test, Jump Relative on True
- BXOR — Bit XOR
- CALL — Call Procedure
- CCF — Complement Carry Flag
- CLR — Clear
- COM — Complement
- CP — Compare
- CPIJE — Compare, Increment, and Jump on Equal
- CPIJNE — Compare, Increment, and Jump on Non-Equal
- DA — Decimal Adjust
- DA — Decimal Adjust (Continued)
- DEC — Decrement
- DECW — Decrement Word
- DI — Disable Interrupts
- DIV — Divide (Unsigned)
- DJNZ — Decrement and Jump if Non-Zero
- EI — Enable Interrupts
- ENTER — Enter
- Figure 6-3 Example of the usage of EXIT statement
- IDLE — Idle Operation
- INC — Increment
- INCW — Increment Word
- IRET — Interrupt Return
- JP — Jump
- JR — Jump Relative
- LD — Load
- LD — Load (Continued)
- LDB — Load Bit
- LDC/LDE — Load Memory
- LDC/LDE — Load Memory (Continued)
- LDCD/LDED — Load Memory and Decrement
- LDCI/LDEI — Load Memory and Increment
- LDCPD/LDEPD — Load Memory with Pre-Decrement
- LDCPI/LDEPI — Load Memory with Pre-Increment
- LDW — Load Word
- MULT — Multiply (Unsigned)
- NEXT — Next
- NOP — No Operation
- OR — Logical OR
- POP — Pop From Stack
- POPUD — Pop User Stack (Decrementing)
- POPUI — Pop User Stack (Incrementing)
- PUSH — Push To Stack
- PUSHUD — Push User Stack (Decrementing)
- PUSHUI — Push User Stack (Incrementing)
- RCF — Reset Carry Flag
- RET — Return
- RL — Rotate Left
- RLC — Rotate Left Through Carry
- RR — Rotate Right
- RRC — Rotate Right Through Carry
- SB0 — Select Bank 0
- SBC — Subtract with Carry
- SCF — Set Carry Flag
- SRA — Shift Right Arithmetic
- RP/SRP0/SRP1 — Set Register Pointer
- STOP — Stop Operation
- SUB — Subtract
- SWAP — Swap Nibbles
- TCM — Test Complement Under Mask
- TM — Test Under Mask
- WFI — Wait for Interrupt
- XOR — Logical Exclusive OR
- CLOCK CIRCUIT
- Clock Status During Power-Down Modes
- RESET AND POWER-DOWN
- MCU Initialization Sequence
- Power-down Modes
- Idle Mode
- Hardware Reset Values
- I/O PORT
- Port 0
- Figure 9-1 Port 0 Control Register High Byte (P0CONH)
- Figure 9-2 Port 0 Control Register Low Byte (P0CONL)
- Figure 9-3 Port 0 Interrupt Control Register (P0INT)
- Figure 9-4 Port 0 Interrupt Pending Register (P0PND)
- Port 1
- Port 2
- Figure 9-6 Port 2 High-Byte Control Register (P2CONH)
- Figure 9-7 Port 2 Low-Byte Control Register (P2CONL)
- BASIC TIMER
- Basic Timer Control Register (BTCON)
- Basic Timer Function Description
- Figure 10-2 Oscillation Stabilization Time on RESET
- Figure 10-3 Oscillation Stabilization Time on STOP Mode Release
- BIT TIMER A
- Functional Description
- Timer A Control Register (TACON)
- Block Diagram of Timer A
- TIMER
- Functional Description of One 16-bit Timer Mode (Timer 0)
- Block Diagram of Timer 0
- Two 8-bit Timers Mode (Timer C and D)
- Figure 12-5 Timer C Prescaler Register (TCPS)
- Functional Description of Two 8-bit Timers Mode (Timer C and D)
- Figure 12-8 Timers C and D Function Block Diagram
- Pulse Width Modulation Mode (Timer D)
- A/D CONVERTER
- Using A/D Pins for Standard Digital Input
- Internal Reference Voltage Levels
- Conversion Timing
- COMPARATOR
- Figure 14-2 CMP Interrupt Mode Control Register (CMPINT)
- Comparator 1/2/3
- Figure 14-7 CMP Interrupt Mode Control Register (CMPINT)
- OPERATIONAL AMPLIFIER
- OPAMP Control Register
- Reference Circuit
- BIT IH-PWM
- Functional Description of 10-bit IH-PWM
- PWM Functional Description
- PWM Control Register (PWMCON)
- PWM CMP linkage Control Register (PWMCCON)
- Block Diagram of PWM Module
- Figure 16-6 Example of the cooperation of PWM and Comparator 0_Delay Trigger
- PROGRAMMABLE BUZZER
- BUZ Frequency Table (@4MHz)
- FLASH MCU ROM
- EMBEDDED FLASH MEMORY INTERFACE
- User Program Mode
- Flash Memory Control Registers (User Program Mode)
- Flash Memory Sector Address Registers
- Sector Erase
- Figure 19-7 Sector Erase Flowchart in User Program Mode
- Programming
- Figure 19-8 Byte Program Flowchart in a User Program Mode
- Figure 19-9 Program Flowchart in a User Program Mode
- Reading
- Hard Lock Protection
- LOW VOLTAGE RESET
- ELECTRICAL DATA
- Table 21-1 Absolute Maximum Ratings
- Figure 21-2 Operating Voltage Range @ External clock
- Figure 21-4 Stop Mode Release Timing When Initiated by a RESET
- Table 21-7 A/D Converter Electrical Characteristics
- Table 21-8 OP AMP Electrical Characteristics
- Table 21-11 Flash Memory AC Electrical Characteristics
- Figure 21-6 Circuit Diagram to Improve the EFT Characteristics
- DEVELOPMENT TOOLS
- Development System Configuration
- TB84B8 Target Board
- Figure 22-5 S3F84B8 Probe Adapter for 20-DIP Package
- Third Parties for Development Tools
- OTP/MTP Programmer (Writer)
- MECHANICAL DATA
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Figure 5-1 S3C8/S3F8 Series Interrupt Types................................................................................................... 5-2Figure 5-2 S3F84B8 Interrupt Structure............................................................................................................. 5-3Figure 5-3 ROM Vector Address Area ............................................................................................................... 5-4Figure 5-4 Interrupt Function Diagram ............................................................................................................... 5-6Figure 5-5 System Mode Register (SYM) .......................................................................................................... 5-8Figure 5-6 Interrupt Mask Register (IMR) .......................................................................................................... 5-9Figure 5-7 Interrupt Request Priority Groups ................................................................................................... 5-10Figure 5-8 Interrupt Priority Register (IPR) ...................................................................................................... 5-11Figure 5-9 Interrupt Request Register (IRQ).................................................................................................... 5-12Figure 6-1 System Flags Register (FLAGS) ...................................................................................................... 6-5Figure 6-2 Example of the Usage of ENTER Statement.................................................................................. 6-40Figure 6-3 Example of the usage of EXIT statement ....................................................................................... 6-41Figure 6-4 Fast interrupt Service Routine ........................................................................................................ 6-45Figure 6-5 Example of the Usage of the NEXT Instruction .............................................................................. 6-59Figure 7-1 Main Oscillator Circuit (RC Oscillator with Internal Capacitor) ......................................................... 7-1Figure 7-2 Main Oscillator Circuit (Crystal/Ceramic Oscillator).......................................................................... 7-1Figure 7-3 System Clock Control Register (CLKCON) ...................................................................................... 7-2Figure 7-4 System Clock Circuit Diagram .......................................................................................................... 7-3Figure 8-1 Low Voltage Reset Circuit ................................................................................................................ 8-2Figure 8-2 Reset Block Diagram ........................................................................................................................ 8-3Figure 8-3 Timing for S3F84B8 after RESET..................................................................................................... 8-3Figure 9-1 Port 0 Control Register High Byte (P0CONH) .................................................................................. 9-3Figure 9-2 Port 0 Control Register Low Byte (P0CONL) ................................................................................... 9-4Figure 9-3 Port 0 Interrupt Control Register (P0INT) ......................................................................................... 9-5Figure 9-4 Port 0 Interrupt Pending Register (P0PND)...................................................................................... 9-6Figure 9-5 Port 1 Control Register (P1CON) ..................................................................................................... 9-8Figure 9-6 Port 2 High-Byte Control Register (P2CONH)................................................................................ 9-10Figure 9-7 Port 2 Low-Byte Control Register (P2CONL) ................................................................................. 9-11Figure 10-1 Basic Timer Control Register (BTCON)........................................................................................ 10-2Figure 10-2 Oscillation Stabilization Time on RESET...................................................................................... 10-4Figure 10-3 Oscillation Stabilization Time on STOP Mode Release ............................................................... 10-5Figure 11-1 Timer A Control Register (TACON) .............................................................................................. 11-4Figure 11-2 Timer A Prescaler Register (TAPS).............................................................................................. 11-5Figure 11-3 Timer A DATA Register (TADATA)............................................................................................... 11-5Figure 11-4 Simplified Timer A Functional Block Diagram .............................................................................. 11-6Figure 12-1 Timer 0 Control Register (TCCON) .............................................................................................. 12-3Figure 12-2 Timer 0 Prescaler Register (TCPS) .............................................................................................. 12-3Figure 12-3 Timer 0 Functional Block Diagram ............................................................................................... 12-4Figure 12-4 Timer C Control Register (TCCON).............................................................................................. 12-6Figure 12-5 Timer C Prescaler Register (TCPS) ............................................................................................. 12-7Figure 12-6 Timer D Prescaler Register (TDPS) ............................................................................................. 12-7Figure 12-7 Timer D Control Register (TDCON).............................................................................................. 12-8Figure 12-8 Timers C and D Function Block Diagram ................................................................................... 12-10Figure 12-9 Timer D PWM Function Block Diagram...................................................................................... 12-11 |
