S3F84B8_UM_REV 1.00 10 BASIC TIMER10-310.2.1 BASIC TIMER FUNCTION DESCRIPTION10.2.1.1 Watchdog Timer FunctionYou can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 toany value other than “1010B”. (The “1010B” value disables the watchdog function.)A reset clears BTCON to “00H”, automatically enabling the watchdog timer function. It also selects the oscillatorclock divided by 4096 as the BT clock.A reset occurs whenever a basic timer counter overflows. During normal operation, the application program mustprevent the overflow and its accompanying reset operation from occurring. To do this, the BTCNT value must becleared (by writing a “1” to BTCON.1) at regular intervals.If a system malfunction occurs due to circuit noise or other error condition, the BT counter clear operation will notbe executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, thebasic timer overflow loop (a bit 7 overflow of 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clearinstruction. If a malfunction occurs, a reset is triggered automatically.10.2.1.2 Oscillation Stabilization Interval Timer FunctionYou can use the basic timer to program a specific oscillation stabilization interval following a reset or when Stopmode has been released by an external interrupt.In the Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value thenstarts increasing at the rate of f OSC/4096 (for reset), or at the rate of preset clock source (for an external interrupt).When BTCNT.7 is set, a signal is generated to indicate that the stabilization interval has elapsed and to gate theclock signal off to the CPU so that it can resume normal operation.In summary, the following events occur when Stop mode is released:1. During Stop mode, an external power-on reset or an external interrupt occurs to trigger the Stop moderelease, leading to the start of oscillation.2. If external power-on reset occurs, the basic timer counter will increase at the rate of fOSC/4096. If an externalinterrupt releases the Stop mode, the BTCNT value increases at the rate of preset clock source.3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set.4. When a BTCNT.7 is set, normal CPU operation is resumed.Figure 10-2 and Figure 10-3 show the oscillation stabilization time on RESET and STOP mode release.
