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Samsung S3F84B8 User Manual Manual pdf 63 page image

Samsung S3F84B8 User Manual

Also see for S3F84B8: Design guide

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. OVERVIEW OF S3F84B8 MICROCONTROLLER
  13. Key Features of S3F84B8
  14. Block Diagram of S3F84B8
  15. Pin Assignments
  16. Pin Descriptions
  17. Table 1-2 Pin Descriptions used to Read/Write the Flash ROM
  18. Pin Circuits
  19. Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)
  20. ADDRESS SPACES
  21. Internal Program Memory (ROM)
  22. Smart Option
  23. Register Architecture
  24. Figure 2-3 Internal Register File Organization in S3F84B8
  25. Register Page Pointer (PP)
  26. Register Set 1
  27. Prime Register Space
  28. Working Registers
  29. Using The Register Points (RP)
  30. Figure 2-8 Non-Contiguous 16 Byte Working Register Block
  31. Register Addressing
  32. Common Working Register Area (C0H–CFH)
  33. Bit Working Register Addressing
  34. Figure 2-13 4-Bit Working Register Addressing Example
  36. Figure 2-15 8-Bit Working Register Addressing Example
  37. System and User Stack
  38. ADDRESSING MODES
  39. Register (R) Addressing Mode
  40. Indirect Register (IR) Addressing Mode
  41. Indirect Register (IR) Addressing Mode (Continued)
  43. Indirect Register (IR) Addressing Mode (Concluded)
  44. Indexed (X) Addressing Mode
  45. Indexed (X) Addressing Mode (Continued)
  46. Indexed (X) Addressing Mode (Concluded)
  47. Direct Address (DA) Mode
  48. Direct Address (DA) Mode (Continued)
  49. Indirect Address (IA) Mode
  50. Relative Address (RA) Mode
  51. Immediate Mode (IM)
  52. CONTROL REGISTERS
  53. ADCON — A/D Converter Control Register: FAH, BANK0
  54. AMTDATA — Anti-mis-trigger Data Register: F6H, BANK0
  55. BUZCON — BUZ Control Register: F7H, BANK0
  56. CLKCON — Clock Control Register: D4H, BANK0
  57. CMP0CON — Comparator0 Control Register: EAH, BANK0
  58. CMP1CON — Comparator1 Control Register: EBH, BANK0
  59. CMP2CON — Comparator1 Control Register: ECH, BANK0
  60. CMP3CON — Comparator1 Control Register: EDH, BANK0
  61. CMPINT — Comparator Interrupt Mode Control Register: EEH, BANK0
  62. FLAGS — System Flags Register: D5H, BANK0
  63. FMCON — Flash Memory Control Register: F5H, BANK1
  64. FMSECL — Flash Memory Sector Address Register (Low Byte): F8H, BANK1
  65. IMR — Interrupt Mask Register: DDH, BANK0
  66. IPH — Instruction Pointer (High Byte): DAH, BANK0
  67. IPR — Interrupt Priority Register: FFH, BANK0
  68. IRQ — Interrupt Request Register: DCH, BANK0
  69. OPACON — OP AMP Control Register: E0H, BANK1
  70. P0CONH — Port 0 Control Register (High Byte): E4H, Bank0
  71. P0CONL — Port 0 Control Register (Low Byte): E5H, BANK0
  72. P0INT — Port 0 Interrupt Control Register: E3H, BANK0
  73. P0PND — Port 0 Interrupt Pending Register: E6H, BANK0
  74. P1CON — Port 1 Control Register: E7H, BANK0
  75. P2CONH — Port 2 Control Register (High Byte): E8H, BANK0
  76. P2CONL — Port 2 Control Register (Low Byte): E9H, BANK0
  77. PWMCON — PWM Control Register: EFH, BANK0
  78. PWMCCON — PWM CMP Control Register: F0H, BANK0
  79. PWMDL — Comparator0 Output Delay Register: F5H, Bank0
  80. RESETID — Reset Source Indicating Register: F2H, BANK1
  81. RP0 — Register Pointer 0: D6H, BANK0
  82. SPL — Stack Pointer: D9H, BANK0
  83. SYM — System Mode Register: DEH, BANK0
  84. TACON — Timer A Control Register: E1H, BANK1
  85. TAPS — TA Pre-scalar Register: E2H, BANK1
  86. TCCON — Timer C Control Register: E5H, BANK1
  87. TCPS — TC Pre-scalar Register: E6H, BANK1
  88. TDCON — Timer D Control Register: E9H, BANK1
  89. TDPS — TD Pre-scalar Register: EAH, BANK1
  90. INTERRUPT STRUCTURE
  91. Interrupt Types
  92. S3F84B8 Interrupt Structure
  93. Interrupt Vector Addresses
  94. System-Level Interrupt Control Registers
  95. Interrupt Processing Control Points
  96. Peripheral Interrupt Control Registers
  97. System Mode Register (SYM)
  98. Interrupt Mask Register (IMR)
  99. Interrupt Priority Register (IPR)
  100. Interrupt Request Register (IRQ)
  101. Interrupt Pending Function Types
  102. Interrupt Source Polling Sequence
  103. Generating Interrupt Vector Addresses
  104. Instruction Pointer (IP)
  105. Procedure for Initiating Fast Interrupts
  106. INSTRUCTION SET
  107. Flags Register (FLAGS)
  108. Flag Descriptions
  109. Instruction Set Notation
  110. Table 6-4 Instruction Notation Conventions
  111. Table 6-5 Opcode Quick Reference
  112. Condition Codes
  113. Instruction Descriptions
  114. ADC — Add with Carry
  115. ADD — Add
  116. AND — Logical AND
  117. BAND — Bit AND
  118. BCP — Bit Compare
  119. BITC — Bit Complement
  120. BITR — Bit Reset
  121. BITS — Bit Set
  122. BOR — Bit OR
  123. BTJRF — Bit Test, Jump Relative on False
  124. BTJRT — Bit Test, Jump Relative on True
  125. BXOR — Bit XOR
  126. CALL — Call Procedure
  127. CCF — Complement Carry Flag
  128. CLR — Clear
  129. COM — Complement
  130. CP — Compare
  131. CPIJE — Compare, Increment, and Jump on Equal
  132. CPIJNE — Compare, Increment, and Jump on Non-Equal
  133. DA — Decimal Adjust
  134. DA — Decimal Adjust (Continued)
  135. DEC — Decrement
  136. DECW — Decrement Word
  137. DI — Disable Interrupts
  138. DIV — Divide (Unsigned)
  139. DJNZ — Decrement and Jump if Non-Zero
  140. EI — Enable Interrupts
  141. ENTER — Enter
  142. Figure 6-3 Example of the usage of EXIT statement
  143. IDLE — Idle Operation
  144. INC — Increment
  145. INCW — Increment Word
  146. IRET — Interrupt Return
  147. JP — Jump
  148. JR — Jump Relative
  149. LD — Load
  150. LD — Load (Continued)
  151. LDB — Load Bit
  152. LDC/LDE — Load Memory
  153. LDC/LDE — Load Memory (Continued)
  154. LDCD/LDED — Load Memory and Decrement
  155. LDCI/LDEI — Load Memory and Increment
  156. LDCPD/LDEPD — Load Memory with Pre-Decrement
  157. LDCPI/LDEPI — Load Memory with Pre-Increment
  158. LDW — Load Word
  159. MULT — Multiply (Unsigned)
  160. NEXT — Next
  161. NOP — No Operation
  162. OR — Logical OR
  163. POP — Pop From Stack
  164. POPUD — Pop User Stack (Decrementing)
  165. POPUI — Pop User Stack (Incrementing)
  166. PUSH — Push To Stack
  167. PUSHUD — Push User Stack (Decrementing)
  168. PUSHUI — Push User Stack (Incrementing)
  169. RCF — Reset Carry Flag
  170. RET — Return
  171. RL — Rotate Left
  172. RLC — Rotate Left Through Carry
  173. RR — Rotate Right
  174. RRC — Rotate Right Through Carry
  175. SB0 — Select Bank 0
  176. SBC — Subtract with Carry
  177. SCF — Set Carry Flag
  178. SRA — Shift Right Arithmetic
  179. RP/SRP0/SRP1 — Set Register Pointer
  180. STOP — Stop Operation
  181. SUB — Subtract
  182. SWAP — Swap Nibbles
  183. TCM — Test Complement Under Mask
  184. TM — Test Under Mask
  185. WFI — Wait for Interrupt
  186. XOR — Logical Exclusive OR
  187. CLOCK CIRCUIT
  188. Clock Status During Power-Down Modes
  189. RESET AND POWER-DOWN
  190. MCU Initialization Sequence
  191. Power-down Modes
  192. Idle Mode
  193. Hardware Reset Values
  194. I/O PORT
  195. Port 0
  196. Figure 9-1 Port 0 Control Register High Byte (P0CONH)
  197. Figure 9-2 Port 0 Control Register Low Byte (P0CONL)
  198. Figure 9-3 Port 0 Interrupt Control Register (P0INT)
  199. Figure 9-4 Port 0 Interrupt Pending Register (P0PND)
  200. Port 1
  201. Port 2
  202. Figure 9-6 Port 2 High-Byte Control Register (P2CONH)
  203. Figure 9-7 Port 2 Low-Byte Control Register (P2CONL)
  204. BASIC TIMER
  205. Basic Timer Control Register (BTCON)
  206. Basic Timer Function Description
  207. Figure 10-2 Oscillation Stabilization Time on RESET
  208. Figure 10-3 Oscillation Stabilization Time on STOP Mode Release
  209. BIT TIMER A
  210. Functional Description
  211. Timer A Control Register (TACON)
  212. Block Diagram of Timer A
  213. TIMER
  214. Functional Description of One 16-bit Timer Mode (Timer 0)
  215. Block Diagram of Timer 0
  216. Two 8-bit Timers Mode (Timer C and D)
  217. Figure 12-5 Timer C Prescaler Register (TCPS)
  218. Functional Description of Two 8-bit Timers Mode (Timer C and D)
  219. Figure 12-8 Timers C and D Function Block Diagram
  220. Pulse Width Modulation Mode (Timer D)
  221. A/D CONVERTER
  222. Using A/D Pins for Standard Digital Input
  223. Internal Reference Voltage Levels
  224. Conversion Timing
  225. COMPARATOR
  226. Figure 14-2 CMP Interrupt Mode Control Register (CMPINT)
  227. Comparator 1/2/3
  228. Figure 14-7 CMP Interrupt Mode Control Register (CMPINT)
  229. OPERATIONAL AMPLIFIER
  230. OPAMP Control Register
  231. Reference Circuit
  232. BIT IH-PWM
  233. Functional Description of 10-bit IH-PWM
  234. PWM Functional Description
  235. PWM Control Register (PWMCON)
  236. PWM CMP linkage Control Register (PWMCCON)
  237. Block Diagram of PWM Module
  238. Figure 16-6 Example of the cooperation of PWM and Comparator 0_Delay Trigger
  239. PROGRAMMABLE BUZZER
  240. BUZ Frequency Table (@4MHz)
  241. FLASH MCU ROM
  242. EMBEDDED FLASH MEMORY INTERFACE
  243. User Program Mode
  244. Flash Memory Control Registers (User Program Mode)
  245. Flash Memory Sector Address Registers
  246. Sector Erase
  247. Figure 19-7 Sector Erase Flowchart in User Program Mode
  248. Programming
  249. Figure 19-8 Byte Program Flowchart in a User Program Mode
  250. Figure 19-9 Program Flowchart in a User Program Mode
  251. Reading
  252. Hard Lock Protection
  253. LOW VOLTAGE RESET
  254. ELECTRICAL DATA
  255. Table 21-1 Absolute Maximum Ratings
  256. Figure 21-2 Operating Voltage Range @ External clock
  257. Figure 21-4 Stop Mode Release Timing When Initiated by a RESET
  258. Table 21-7 A/D Converter Electrical Characteristics
  259. Table 21-8 OP AMP Electrical Characteristics
  260. Table 21-11 Flash Memory AC Electrical Characteristics
  261. Figure 21-6 Circuit Diagram to Improve the EFT Characteristics
  262. DEVELOPMENT TOOLS
  263. Development System Configuration
  264. TB84B8 Target Board
  265. Figure 22-5 S3F84B8 Probe Adapter for 20-DIP Package
  266. Third Parties for Development Tools
  267. OTP/MTP Programmer (Writer)
  268. MECHANICAL DATA
Samsung S3F84B8 User Manual Manual pdf 63 page image
S3F84B8_UM_REV 1.00 3 ADDRESSING MODES3-133.13 RELATIVE ADDRESS (RA) MODEIn Relative Address (RA) mode, a two’s complement signed displacement between - 128 and + 127 is specified inthe instruction. The displacement value is then added to the current PC value. Its result is the address of nextinstruction to be executed. Before this addition occurs, the PC contains the address of instruction immediatelyfollowing the current instruction.Several program control instructions use the Relative Address mode to perform conditional jumps. Theinstructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.OPCODEProgram MemoryDisplacementProgram MemoryAddress UsedSample Instructions:JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128Next OPCODE+SignedDisplacement ValueCurrent InstructionCurrentPC ValueFigure 3-13 Relative Addressing
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