S3F84B8All-in-One IH CookerRevision 0.00May 2010AApppplliiccaattiioonn NNoottee 2010 Samsung Electronics Co., Ltd. All rights reserved.

OVERVIEW OF IH COOKER (IHC)

Key Features of S3F84B8

System Principle

HARDWARE IMPLEMENTATION

Table 2-1 S3F84B8 pin assignment in IH cooker system

Power Supply

Synchronization Circuit

Figure 2-4 Waveform of the Synchronization Circuit

Power control

Current Measurement

System Protection

Temperature Protection

Other Functions

Key and Display Circuit

SOFTWARE IMPLEMENTATION

Software Diagram

Internal Resource Arrangement and Configuration

Error Code

Samsung S3F84B8 Design Manual

S3F84B8

OVERVIEW OF S3F84B8 MICROCONTROLLER

Block Diagram of S3F84B8

Pin Assignments

Pin Descriptions

Table 1-2 Pin Descriptions used to Read/Write the Flash ROM

Pin Circuits

Figure 1-5 Pin Circuit Type 1-1 (P1.0-1.2, P2.0-2.2, P2.4-2.7)

ADDRESS SPACES

Internal Program Memory (ROM)

Smart Option

Register Architecture

Figure 2-3 Internal Register File Organization in S3F84B8

Register Page Pointer (PP)

Register Set 1

Prime Register Space

Working Registers

Using The Register Points (RP)

Figure 2-8 Non-Contiguous 16 Byte Working Register Block

Register Addressing

Common Working Register Area (C0H–CFH)

Bit Working Register Addressing

Figure 2-13 4-Bit Working Register Addressing Example

Figure 2-15 8-Bit Working Register Addressing Example

System and User Stack

ADDRESSING MODES

Register (R) Addressing Mode

Indirect Register (IR) Addressing Mode

Indirect Register (IR) Addressing Mode (Continued)

Indirect Register (IR) Addressing Mode (Concluded)

Indexed (X) Addressing Mode

Indexed (X) Addressing Mode (Continued)

Indexed (X) Addressing Mode (Concluded)

Direct Address (DA) Mode

Direct Address (DA) Mode (Continued)

Indirect Address (IA) Mode

Relative Address (RA) Mode

Immediate Mode (IM)

CONTROL REGISTERS

ADCON — A/D Converter Control Register: FAH, BANK0

AMTDATA — Anti-mis-trigger Data Register: F6H, BANK0

BUZCON — BUZ Control Register: F7H, BANK0

CLKCON — Clock Control Register: D4H, BANK0

CMP0CON — Comparator0 Control Register: EAH, BANK0

CMP1CON — Comparator1 Control Register: EBH, BANK0

CMP2CON — Comparator1 Control Register: ECH, BANK0

CMP3CON — Comparator1 Control Register: EDH, BANK0

CMPINT — Comparator Interrupt Mode Control Register: EEH, BANK0

FLAGS — System Flags Register: D5H, BANK0

FMCON — Flash Memory Control Register: F5H, BANK1

FMSECL — Flash Memory Sector Address Register (Low Byte): F8H, BANK1

IMR — Interrupt Mask Register: DDH, BANK0

IPH — Instruction Pointer (High Byte): DAH, BANK0

IPR — Interrupt Priority Register: FFH, BANK0

IRQ — Interrupt Request Register: DCH, BANK0

OPACON — OP AMP Control Register: E0H, BANK1

P0CONH — Port 0 Control Register (High Byte): E4H, Bank0

P0CONL — Port 0 Control Register (Low Byte): E5H, BANK0

P0INT — Port 0 Interrupt Control Register: E3H, BANK0

P0PND — Port 0 Interrupt Pending Register: E6H, BANK0

P1CON — Port 1 Control Register: E7H, BANK0

P2CONH — Port 2 Control Register (High Byte): E8H, BANK0

P2CONL — Port 2 Control Register (Low Byte): E9H, BANK0

PWMCON — PWM Control Register: EFH, BANK0

PWMCCON — PWM CMP Control Register: F0H, BANK0

PWMDL — Comparator0 Output Delay Register: F5H, Bank0

RESETID — Reset Source Indicating Register: F2H, BANK1

RP0 — Register Pointer 0: D6H, BANK0

SPL — Stack Pointer: D9H, BANK0

SYM — System Mode Register: DEH, BANK0

TACON — Timer A Control Register: E1H, BANK1

TAPS — TA Pre-scalar Register: E2H, BANK1

TCCON — Timer C Control Register: E5H, BANK1

TCPS — TC Pre-scalar Register: E6H, BANK1

TDCON — Timer D Control Register: E9H, BANK1

TDPS — TD Pre-scalar Register: EAH, BANK1

INTERRUPT STRUCTURE

Interrupt Types

S3F84B8 Interrupt Structure

Interrupt Vector Addresses

System-Level Interrupt Control Registers

Interrupt Processing Control Points

Peripheral Interrupt Control Registers

System Mode Register (SYM)

Interrupt Mask Register (IMR)

Interrupt Priority Register (IPR)

Interrupt Request Register (IRQ)

Samsung S3F84B8 Design Manual

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