S3F84B8_UM_REV 1.00 5 INTERRUPT STRUCTURE5-165.1.18 INSTRUCTION POINTER (IP)The instruction pointer (IP) is adopted by all the S3C8/S3F8 series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. Thenames of IP registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).5.1.19 FAST INTERRUPT PROCESSINGThe feature called fast interrupt processing allows an interrupt within a given level to be completed inapproximately 6 clock cycles, rather than the usual 16 clock cycles. To select a specific interrupt level for fastinterrupt processing, write the appropriate 3-bit value to SYM.4–SYM.2. Thereafter, to enable fast interruptprocessing for the selected level, set SYM.1 to “1”.Two other system registers support fast interrupt processing: The instruction pointer (IP) contains the starting address of service routine (and is later used to swap theprogram counter values) When a fast interrupt occurs, the contents of FLAGS register are stored in an unmapped, dedicated registercalled FLAGS’ (“FLAGS prime”).NOTE: For the S3F84B8 microcontroller, the service routine for any one of the eight interrupt levels (IRQ0–IRQ7) can beselected for fast interrupt processing.
