S3F84B8_UM_REV 1.00 6 INSTRUCTION SET6-366.3.24 DI — DISABLE INTERRUPTSDIOperation: SYM (0) 0Bit zero of the system mode control register, SYM.0, is cleared to “0”, globally disabling allinterrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,but the CPU will not service them if interrupt processing is disabled.Flags: No flags are affected.Format:Bytes Cycles Opcode(Hex)opc 1 4 8FExample: Given SYM = 01H:DIIf the value of SYM register is 01H, statement “DI” leaves the new value 00H in register andclears SYM.0 to “0”, disabling interrupt processing.Before changing IMR, interrupt pending, and interrupt source control register, ensure that allinterrupts are disabled.
