S3F84B8_UM_REV 1.00 4 CONTROL REGISTERS4-64.1.2 AMTDATA — ANTI-MIS-TRIGGER DATA REGISTER: F6H, BANK0Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESET Value 0 0 0 0 0 0 0 0Read/Write R/W R/W R/W R/W R/W R/W R/W R/WAddressing Mode Register addressing mode only.7–.0 Anti-mis-trigger time= (AMTDATA 4)/fpwmclk + TSTNOTE: 0 < TST (setting time) < 4/fpwmclk4.1.3 BTCON — BASIC TIMER CONTROL REGISTER: D3H, BANK0Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0RESET Value 0 0 0 0 0 0 0 0Read/Write R/W R/W R/W R/W R/W R/W R/W R/WWatchdog Timer Function Enable Bit1 0 1 0 Disables watchdog timer function..7–.4Others Enables watchdog timer function.Basic Timer Input Clock Selection Code0 0 fOSC /40960 1 fOSC /10241 0 fOSC /128.3–.21 1 Invalid settingBasic Timer 8-Bit Counter Clear Bit0 No effect..11 Clears the basic timer counter value.Basic Timer Divider Clear Bit0 No effect..01 Clears both the dividers.NOTE: When you write a “1” to BTCON.0 (or BTCON.1), the basic timer divider (or basic timer counter) is cleared. The bit isthen automatically cleared to “0”.
