S3F84B8_UM_REV 1.00 14 COMPARATOR14-5CMP1 Control Register (CMP1CON)EBH, Set1, Bank0, Reset = 02H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP1 status bit0 = CMP1_N > CMP1_P1 = CMP1_N < CMP1_PCMP 1 interrupt pending bit:0 = No interrupt pending(Clear pending bit when write)1 = Interrupt is pendingCMP1 Interrupt enable bit0 = Disable interrupt1 = Enable interruptCMP 1 output polarity select bit0 = CMP1 output is not inverted1 = CMP1 output is invertedCMP1 enable bit0 = Disable comparator1 = Enable comparatorCMP 1 reference level select bit000 = 0.45VDD001 = 0.50VDD010 = 0.55VDD011 = 0.60VDD100 = 0.65VDD101 = 0.70VDD110 = 0.75VDD111 = 0.80VDDNOTE: Please refer to the programming tip for proper configuration sequence.Figure 14-4 CMP1 Control Register (CMP1CON)CMP2 Control Register (CMP2CON)ECH, Set1, Bank0, Reset = 02H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP2 status bit0 = CMP2_N > CMP2_P1 = CMP2_N < CMP2_PCMP 2 interrupt pending bit:0 = No interrupt pending(Clear pending bit when write)1 = Interrupt is pendingCMP2 Interrupt enable bit0 = Disable interrupt1 = Enable interruptCMP 2 output polarity select bit0 = CMP2 output is not inverted1 = CMP2 output is invertedCMP2 enable bit0 = Disable comparator1 = Enable comparatorCMP 2 reference level select bit000 = 0.45VDD001 = 0.50VDD010 = 0.55VDD011 = 0.60VDD100 = 0.65VDD101 = 0.70VDD110 = 0.75VDD111 = 0.80VDDNOTE: Please refer to the programming tip for proper configuration sequence.Figure 14-5 CMP2 Control Register (CMP2CON)
