S3F84B8_UM_REV 1.00 14 COMPARATOR14-414.1.1.2 Comparator 1/2/3Comparator 1, 2, and 3 have the same structure. Their positive input is internally connected with referencevoltage, programmable from 0.45VDD to 0.8VDD with the step length of 0.05VDD.The output (falling edge) of comparator 1, 2, and 3 can be configured to generate PWM hard lock trigger signal(PWMCCON.1–.2/.3-0.4/.5/.6 = 11) or soft lock trigger signal (PWMCCON.1–.2/.3–0.4/.5/.6 = 01).In case of hard lock, PWM output will stop immediately (stop voltage level is determined by PWM output polaritybit, that is, when PWMCON.5 = 0, PWM output is ‘0’ and when PWMCON.5 = 1, PWM output is ‘1’). To unlock thehard lock, write ‘1’ to PWMCON.3.On the other hand, in case of soft lock, PWM output will stop immediately (stop voltage level is determined byPWM output polarity bit, that is, when PWMCON.5 = 0, PWM output is ‘0’ and when PWMCON.5 = 1, PWM outputis ‘1’). The PWM output will then reload PWMDATA with PWMPDATA. Soft lock will be automatically unlocked inthe next PWM cycle.14.1.1.2.1 Comparator Control Register (CMP1CON, COM2CON, CMP3CON)You can use comparator control registers for the following purposes: Select comparator reference voltage Enable comparator Enable comparator interrupt Set comparator output polarity Check comparator status Clear interrupt pending bitCMP1CON, CMP2CON, and CMP3CON are located at address EBH, ECH, and EDH, Set1 Bank0, and areread/write addressable (except CMP1/2/3CON.1) using Register addressing mode.To enable comparator1/2/3, you must write ‘1’ to CMP1/2/3CON.3. The positive input of comparator is internallyconnected with reference voltage, programmable from 0.45VDD to 0.8VDD with step length of 0.05VDD.The output polarity is programmable by configuring CMP1/2/3CON.4.CMP1/2/3CON.1 represents the real status of two inputs, read as ‘0’ when CMP1/2/3_N > reference voltage or ‘1’when CMP1/2/3_N < reference voltage.Comparator 1/2/3 can generate an interrupt to indicate the alternation of two input pins. You can choose the fallingedge, rising edge, or falling and rising edge to trigger the comparator interrupt by configuring CMPINT register. Toenable the interrupt, write ‘1’ in CMP1/2/3CON.2. On the other hand, to clear the interrupt pending bit, write ‘0’ toCMP1/2/3CON.0. The interrupt pending bit must be cleared by the software.
