S3F84B8_UM_REV 1.00 12 TIMER 012-8Timer B Control Register (TDCON)E9H, Set1, Bank1, Reset = 00H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBTimer D counter clear bit:0 = No effect1 = Clear the timer D counter(when write)Timer D operating mode selection bits:00 = Interval mode01 = 6-bit PWM mode (OVF interrupt can occur)10 = 7-bit PWM mode (OVF interrupt can occur)11 = 8-bit PWM mode (OVF interrupt can occur)Timer D overflow interrupt pending bit0 = no interrupt pending(clear pending bit when write)1 = interrupt pendingTimer D match interrupt pending bit0 = no interrupt pending(clear pending bit when write)1 = interrupt pendingTimer D match interrupt enable bit:0 = Disable match interrupt1 = Enable match interruptTimer D overflow interrupt enable bit:0 = Disable overflow interrupt1 = Enable overflow interruptTimer D count enable bit:0 = Disable counting operating1 = Enable counting operatingFigure 12-7 Timer D Control Register (TDCON)
