S3F84B8_UM_REV 1.00 14 COMPARATOR14-6CMP3 Control Register (CMP3CON)EDH, Set1, Bank0, Reset = 02H, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP3 status bit0 = CMP3_N > CMP3_P1 = CMP3_N < CMP3_PCMP 3 interrupt pending bit:0 = No interrupt pending(Clear pending bit when write)1 = Interrupt is pendingCMP3 Interrupt enable bit0 = Disable interrupt1 = Enable interruptCMP 3 output polarity select bit0 = CMP3 output is not inverted1 = CMP3 output is invertedCMP3 enable bit0 = Disable comparator1 = Enable comparatorCMP 3 reference level select bit000 = 0.45VDD001 = 0.50VDD010 = 0.55VDD011 = 0.60VDD100 = 0.65VDD101 = 0.70VDD110 = 0.75VDD111 = 0.80VDDNOTE: Please refer to the programming tip for proper configuration sequence.Figure 14-6 CMP3 Control Register (CMP3CON)CMP Interrupt Mode Control Register (CMPINT)EDH, Set1, Bank0, Reset = FFH, R/W.7 .6 .5 .4 .3 .2 .1 .0MSB LSBCMP3 interrupt mode selection0 0 = invalid setting01 = Falling edge10 = Rising edge11 = Falling and rising edgeCMP2 interrupt mode selection0 0 = invalid setting01 = Falling edge10 = Rising edge11 = Falling and rising edgeCMP0 interrupt mode selection0 0 = invalid setting01 = Falling edge10 = Rising edge11 = Falling and rising edgeCMP1 interrupt mode selection0 0 = invalid setting01 = Falling edge10 = Rising edge11 = Falling and rising edgeFigure 14-7 CMP Interrupt Mode Control Register (CMPINT)
