S3F84B8_UM_REV 1.00 14 COMPARATOR14-114 COMPARATOR14.1 OVERVIEW OF COMPARATORThe S3F84B8 microcontroller has four comparators (Comparator 0, 1, 2, and 3). The operation of these fourcomparators is controlled by four registers, namely, CMP0CON, CMP1CON, CMP2CON, and CMP3CON. Theinterrupt control register (CMPINT) controls the interrupt mode of four comparators.14.1.1 FUNCTIONAL DESCRIPTION OF COMPARATOR14.1.1.1 Comparator 0In Comparator 0, both positive and negative inputs act as chip pins. The polarity of comparator 0 output can beset to inverted or non-inverted. You could check the real input status by reading CMP0CON.1.The output (falling edge) can be configured as trigger signal to start a new PWM cycle when the PWM-CMP0linkage is enabled by writing ‘1’ to PWMCCON.0. It can have a programmable delay to realize delay trigger byconfiguring the AMTDATA register, which is useful when realizing timing adjustment.14.1.1.1.1 Comparator 0 Control Register (CMP0CON)You can use comparator 0 control register (CMP0CON) for the following purposes: Enable comparator 0 Enable comparator 0 interrupt Set comparator 0 output polarity Check comparator 0 input status Clear interrupt pending bitCMP0CON is located at address EAH, Set1 Bank0, and is read/write addressable (except CMP0CON.1) usingRegister addressing mode.To enable comparator0, you must write ‘1’ to CMP0CON.3. The output polarity is programmable by configuringCMP0CON.4.CMP0CON.1 represents the real status of two inputs, read as ‘0’ when CMP0_N > CMP0_P or ‘1’ when CMP0_N< CMP0_P.Comparator 0 can generate an interrupt to indicate the alternation of two input pins. The interrupt trigger mode(rising/falling/rising and falling edge) can be configured in CMPINT register. To enable the interrupt, write ‘1’ inCMP0CON.2. On the other hand, to clear the interrupt pending bit, write ‘0’ to CMP0CON.0. The interrupt pendingbit must be cleared by the software.
