S3F84B8_UM_REV 1.00 6 INSTRUCTION SET6-146.3.2 ADD — ADDADD dst,srcOperation: dst dst + srcThe source operand is added to the destination operand. Their sum is stored in the destination.The contents of source remain unaffected. Two’s-complement addition is performed.Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise.Z: Set if the result is “0”; cleared otherwise.S: Set if the result is negative; cleared otherwise.V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the resultis of the opposite sign; cleared otherwise.D: Always cleared to “0”.H: Set if a carry from the low-order nibble occurred.Format:Bytes Cycles Opcode(Hex)Addr Modedst srcopc dst | src 2 4 02 r r6 03 r lropc src dst 3 6 04 R R6 05 R IRopc dst src 3 6 06 R IMExamples: Given R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, and register 03H = 0AH:ADD R1,R2 R1 = 15H, R2 = 03HADD R1,@R2 R1 = 1CH, R2 = 03HADD 01H,02H Register 01H = 24H, register 02H = 03HADD 01H,@02H Register 01H = 2BH, register 02H = 03HADD 01H,#25H Register 01H = 46HIn the first example, destination working register R1 contains the value 12H and source workingregister R2 contains the value 03H. The statement “ADD R1,R2” adds 03H to 12H, leaving thevalue 15H in register R1.
