March 2000 © TOSHIBA TEC 7-55 DP120F/DP125F Circuit Description• DMAC GA Signal Table (2/7)No. Signal Name Type Functions18 MWRHX O SRAM write signal (active-low)Write signal for SRAM (IC31).19 MWRLX O SRAM write signal (active-low)Write signal for SRAM (IC30).20 MWRX O Flash ROM write signal (active-low)Write signal for Flash ROM (IC13, IC20).21-27, 29-32 SDA0-9 O System address busAddress bus for SYS-DRAM (IC34, IC41), SYS-DRAM (IC46), DRAM (IC1, IC2) on the Memory PBA.33 SRAS0 O System RAS0 signalRAS signal for SYS-DRAM (IC34, IC41) and SYS-DRAM (IC46).34 SRAS1 O System RAS 1 signalRAS signal for DRAM (IC1, IC2) on the Memory PBA.35, 37 SCAS0L, H O System CAS0L and CAS0H signalsCAS signals for SYS-DRAM (IC34), SYS-DRAM(IC46), and DRAM (IC1) on the Memory PBA.38, 39 SCAS1L, H O System CAS1L and CAS1H signalsCAS signals for SYS-DRAM (IC41) and DRAM (IC2)on the Memory PBA.40 SDOEX O System read signalRead signal for SYS-DRAM (IC34, IC41), SYS-DRAM (IC46), and DRAM (IC1, IC2) on the MemoryPBA.41 SDWEX O System write signalWrite signal for SYS-DRAM (IC34, IC41), SYS-DRAM (IC46), and DRAM (IC1, IC2) on the MemoryPBA.42, 79, 102, 3.3V - +3.3V113, 121,131, 141,181, 21043 BGACKX O Bus ground acknowledge signal (active-low)Indicates the fact of becoming the bus master to theCPU (IC66).44 BRX O Bus request signal (active-low)Requests the CPU for bus control.I: Input O: Output I/O: Bidirectional
