Section 5: Pulse measure and pulse generator units Model 4200A-SCS Parameter Analyzer Reference Manual5-36 4200A-901-01 Rev. C / February 2017Note that after the first action, "Output Pulse Burst," all pulse channels in the test stop pulsing andoutput 0 V while performing the actions in the remaining boxes in the diagram. The time betweenpulses is determined by the time required to process the measurements and perform the calculationsand comparisons shown in the previous figure. Wider pulses, longer pulse periods, and a highernumber of pulses increases the time between pulses where the output is at 0 V. Note that both PulseI-V and Waveform Capture Test modes use this algorithm and both will output 0 V between pulses foreach step in a sweep. For strict control over the pulse voltage versus time, see the Segment Arbfeature of the PMU.The "Get Good Measurement" step shown in the previous figure also must ensure that the currentmeasure range is correct (if ranging is enabled) and check the measured voltage and current againstthe thresholds. See PMU - all terminal parameters (on page 6-70).There are two parameters that control how the LLEC algorithm functions: Maximum number ofiterations and tolerance window. For ITMs, the maximum number of iterations is fixed at 20 and thetolerance window is 0.3 percent. For UTMs, use the setmode (on page 13-182) function. The LLECalgorithm will iterate, trying to reach the target voltage until one of the following occurs: 1) The targetvoltage is reached (within tolerance specified) or 2) maximum number of iterations is reached. Themaximum number of iterations must be equal for each channel in the test.Coping with the load-line effectThere are several ways of working with this effect. The simplest one is to program the DUT load intothe pulse card channel using the pulse_load (on page 13-145) command, or setting the Pulse Loadvalue in the KPulse (on page 10-1) virtual front panel. The pulse card will calculate the appropriateVINT to output so that the V DUT pulse waveform, specified by pulse_vlow and pulse_vhigh, hasthe correct levels. This works well for high impedance devices or device terminals (R DUT = 1 kΩ), suchas the gate terminal on a CMOS field effect transistor (FET). Unfortunately, many times R DUT is notknown or varies. A key example of a varying R DUT is the drain-source resistance during a VD -IDsweep, where R DS is changing from point-to-point and sweep-to-sweep.There is basically only one way to handle this situation, with two different levels of implementation. Ingeneral, assume the DUT is a FET. If the test consists of a single, or limited number of gate anddrain, test points, the necessary voltages can be determined by pre-characterizing each unique set oftest conditions.This pre-characterization requires some way to measure the pulse heights, which is typically doneusing an oscilloscope and an iterative trial and error approach. Each test voltage needs to bemeasured, with the pulse levels adjusted until the correct voltage is reached. Record each pulse levelrequired to reach the required VDUT levels.The 4225-PMU has built-in load-line effect compensation. For details, see Load-line effectcompensation (LLEC) for the PMU (on page 5-34).
