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GE PACSystems RX7i Reference Manual

Also see for PACSystems RSTi-EP: User manualCPU Programmer's Reference Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Chapter 1 Introduction
  9. Revisions in this Manual
  10. PACSystems Control System Overview
  11. PACSystems CPU Models
  12. RX3i Overview
  13. RX7i Overview
  14. RSTi-EP Overview
  15. Migrating Series 90 Applications to PACSystems
  16. Documentation
  17. Chapter 2 CPU Features & Specifications
  18. Common CPU Features
  19. Features Shared by Certain PACSystems CPU Models
  20. Firmware Storage in Flash Memory
  21. Embedded PROFINET Controller
  22. OPC UA
  23. Removable Data Storage Devices (RDSDs)
  24. CPU Over-Temperature Monitoring and Behavior
  25. RX3i CPU Features and Specifications
  26. CPE400
  27. Figure 3: CPE400 Underside Ports & Connectors
  28. Figure 4: CPE400 Micro-SD & USB Pinouts
  29. Figure 5: Typical Field Agent Application
  30. Figure 6: Login to Predix
  31. Figure 7: Predix Change Password
  32. Figure 9: Technician Console, Network Configuration
  33. Figure 10: Enter Proxy Server Address
  34. Figure 12: Technician Console, Time Sync Configuration
  35. Figure 13: LAN3 Interconnects for Hot Standby Redundancy
  36. Figure 14: Display Port Connector
  37. Figure 15: Location of RTC battery on CPE400
  38. Figure 16: DIN-Rail Mount Bracket Assembly CPE400
  39. CPE330
  40. Figure 19: CPE330 RUN/STOP Switch and RDSD Switches
  41. CPE302, CPE305 and CPE310
  42. Figure 23: External Features of CPE302/CPE305
  43. Figure 25: Accessing Real-Time Clock Battery (CPE302, CPE305 and CPE310)
  44. Figure 26: Sample Tool for Coin Battery Extraction
  45. CPU315 and CPU320/CRU320
  46. CPU310
  47. RX7i CPU Features and Specifications
  48. CPE030/CRE030 and CPE040/CRE040
  49. CPE010, CPE020 and CRE020
  50. RX7i Embedded Ethernet Interface
  51. RSTi-EP CPU Features and Specifications
  52. CPE100/CPE115
  53. Figure 32: CPE100/CPE115 Membrane Pushbutton and Module Status LEDs
  54. Figure 34: Typical Multi-Tier LAN Application (Star/Bus Topology)
  55. Chapter 3 CPU Configuration
  56. Configuring the CPU
  57. Configuration Parameters
  58. Modbus TCP Address Map
  59. SNTP
  60. Time
  61. Scan Parameters
  62. Memory Parameters
  63. Fault Parameters
  64. Redundancy Parameters (Redundancy CPUs Only)
  65. COM1 and COM2 Parameters
  66. Scan Sets Parameters
  67. Access Control
  68. OPC UA Parameters
  69. Storing (Downloading) Hardware Configuration
  70. Configuring the Embedded Ethernet Interface
  71. Establishing Initial Ethernet Communications
  72. Setting a Temporary IP Address
  73. Chapter 4 CPU Operation
  74. CPU Sweep
  75. Parts of the CPU Sweep
  76. CPU Sweep Modes
  77. Figure 42: Typical Sweeps in Constant Sweep Mode
  78. Program Scheduling Modes
  79. Window Modes
  80. Data Coherency in Communications Windows
  81. Run/Stop Operations
  82. CPU STOP Modes
  83. STOP-to-RUN Mode Transition
  84. Flash Memory Operation
  85. Logic/Configuration Source and CPU Operating Mode at Power-Up
  86. CPU Mode when Memory Not Preserved/Power-up Source is Flash
  87. CPU Mode when Memory Preserved
  88. Clocks and Timers
  89. Time-of-Day Clock
  90. Watchdog Timer
  91. System Security
  92. Passwords and Privilege Levels - Legacy Mode
  93. OEM Protection – Legacy Mode
  94. Enhanced Security for Passwords and OEM Protection
  95. Legacy/Enhanced Security Comparison
  96. PACSystems I/O System
  97. I/O Configuration
  98. Genius I/O
  99. I/O System Diagnostic Data Collection
  100. Power-Up and Power-Down Sequences
  101. Power-Down Sequence
  102. Power Cycle Operation with an Energy Pack
  103. Retention of Data Memory Across Power Failure
  104. Chapter 5 Communications
  105. Ethernet Communications
  106. Figure 45: CPE330 Overlapping Local IP Subnet Example
  107. Figure 46: Expected Response Path
  108. Ethernet Interface Modules
  109. Serial Communications
  110. Configurable STOP Mode Protocols
  111. Serial Port Pin Assignments
  112. Figure 48: COM1 Port CPE400
  113. Serial Port Electrical Isolation
  114. Serial Cable Lengths and Shielding
  115. Serial Port Baud Rates
  116. Series 90-70 Communications and Intelligent Option Modules
  117. Programmable Coprocessor Module (PCM)
  118. DLAN/DLAN+ (Drives Local Area Network) Interface
  119. Chapter 6 Serial I/O, SNP & RTU Protocols
  120. Configuring Serial Ports Using COMMREQ Function 65520
  121. Invalid Port Configuration Combinations
  122. COMMREQ Command Block Parameter Values
  123. Example COMMREQ Command Blocks for Serial Port Setup function
  124. Serial I/O Protocol
  125. Serial I/O COMMREQ Commands
  126. Overlapping COMMREQs
  127. Initialize Port Function (4300)
  128. Set Up Input Buffer Function (4301)
  129. Flush Input Buffer Function (4302)
  130. Read Port Status Function (4303)
  131. Write Port Control Function (4304)
  132. Cancel COMMREQ Function (4399)
  133. Autodial Function (4400)
  134. Write Bytes Function (4401)
  135. Read Bytes Function (4402)
  136. Read String Function (4403)
  137. RTU Slave Protocol
  138. Message Format
  139. Figure 50: RTU Read Output Table Example
  140. Cyclic Redundancy Check (CRC)
  141. RTU Message Descriptions
  142. Figure 53: RTU Read Input Table Message Format
  143. Figure 54: RTU Read Registers Message Format
  144. Figure 55: RTU Read Analog Inputs Message Format
  145. Figure 56: RTU Force Single Output Message Format
  146. Figure 57: RTU Preset Single Register Message Format
  147. Figure 58: RTU Read Exception Status Message Format
  148. Figure 59: RTU Loopback/Maintenance Message Format
  149. Figure 60: RTU Force Multiple Outputs Message Format
  150. Figure 61: RTU Preset Multiple Registers Message Format
  151. Figure 62: RTU Report Device Type Message Format
  152. Figure 63: RTU Read Scratch Pad Memory Message Format
  153. RTU Scratch Pad
  154. Communication Errors
  155. RTU Slave/SNP Slave Operation with Programmer Attached
  156. SNP Slave Protocol
  157. Appendix A Performance Data
  158. A-1 Boolean Execution Times
  159. A-2 Instruction Timing
  160. A-2.2 PLC Version Information
  161. A-2.3 RX3i & RSTi-EP Instruction Times
  162. A-2.4 RX7i Instruction Times
  163. A-3 Overhead Sweep Impact Times
  164. A-3.1 Base Sweep Times
  165. A-3.2 What the Sweep Impact Tables Contain
  166. A-3.3 Programmer Sweep Impact Times
  167. A-3.4 I/O Scan and I/O Fault Sweep Impact
  168. A-3.5 Ethernet Global Data Sweep Impact
  169. A-3.6 EGD Sweep Impact for Embedded Ethernet Interface on RX3i & RSTi-EP CPE Models
  170. A-3.7 Sweep Impact of Intelligent Option Modules
  171. A-3.8 I/O Interrupt Performance and Sweep Impact
  172. Figure 65: Interrupt Execution Considerations
  173. A-3.9 Timed Interrupt Performance
  174. A-3.10 Example of Predicted Sweep Time Calculation
  175. Appendix B User Memory Allocation
  176. B-1 Items that Count Against User Memory
  177. B-2 User Program Memory Usage
/ 317
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This manual is suitable for:
PACSystems RSTi-EPPACSystems RX7iPACSystems* RX3i