Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User’s Guide UART26/17/03 20-2720.3.2.16 Receive Command RegisterRegister Bank: 1RCM is the Receive Command Register. The RCM Register controls the operation of thereceive machine. The active bits used in this register are Write Only.NOTE: The reset value of this register’s bits is indeterminate .Table 20-41. RCM RegisterBIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16FIELD ///RESET — — — — — — — — — — — — — — — —RW R R R R R R R R R R R R R R R RBIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0FIELD /// RXE RXDI FRM FRF LRF ORF ///RESET — — — — — — — — — — — — — — — —RW R R R R R R R R W W W W W W R RADDR 0xFFFC2000 + 0x14Table 20-42. RCM Register DefinitionsBITS NAME DESCRIPTION31:8 /// Reserved Do not modify. Read as zero.7 RXE Receive Enable1 = Enables the reception of characters.6 RXDIReceive Disable1 = Disables the reception of data on RXD pin. RxDI takes priority over RxE indisabling the reception of characters.5 FRMFlush Receive Machine1 = Resets the receiver logic, except registers and FIFOs, enables reception, andunlocks the receive FIFO.4 FRF Flush Receive FIFO Setting this bit clears the Rx FIFO.3 LFRLock Rx FIFO1 = Disables the write mechanism of the Rx FIFO, so that characters subsequent-ly received are lost (not written to the Rx FIFO). Reception is not disabled andcomplete status/event reporting continues.Use this command in the μLAN Mode to disable loading of characters into theRxFIFO, until an address match is detected. LRF takes priority over ORF inlocking Rx FIFO.2 ORF Open (unlock) Rx FIFO1 = Enables (unlocks) the Rx FIFO write mechanism.1:0 /// Reserved Read as zero.