Sharp Blue Treak LH75400 User Manual

Vectored Interrupt Controller LH75400/01/10/11 (Preliminary) User’s Guide10-4 6/17/0310.1.5 Clearing InterruptsWhile the procedure for clearing an interrupt varies from source to source, general clearingactions must be performed:1. The interrupt must be cleared at its source, regardless of whether the interrupt sourceis external, internal, or software generated.– If an interrupt source is external and configured as edge triggered, the interruptmust be cleared in the RCPC IntClear Register (see Section 9.3.2.14).– If an interrupt source is external and configured as level triggered, the interruptmust be cleared, reset, or disabled at its source external to the SoC.– If the interrupt source is a software command, the interrupt must be cleared usingthe SoftIntClear Register (described under Section 10.2.2.8).– If the interrupt source is internal, the interrupt must be cleared in a way appropriateto the internal source. Usually this involves setting a bit or clearing a bit in a ‘clear-ing’ register specific to the particular internal source. For example, the DMAController has a Clr Register that must be written with a value specific to the DMAController. Other devices within the SoC have similar device-specific ways of clear-ing an interrupt generated by that device. See the appropriate chapter in this Tech-nical Data Sheet for information about clearing each device.2. The interrupt must be cleared within the VIC by writing any value to the VectAddrRegister (described in Section 10.2.2.9). Writing a value of ‘0’ is recommended. Thisaction signals the hardware vector address and priority logic that it can assert a newinterrupt and its associated address.10.1.6 PriorityThe VIC can assert an FIQ interrupt and an IRQ interrupt simultaneously. When thisoccurs, the CPU gives the FIQ priority over the IRQ interrupt. Priority arbitration for simul-taneously invoked IRQ interrupts is performed in the VIC hardware.The priority of IRQ interrupt sources is:• All vectored interrupts have priority over default-vectored interrupts• Vectored interrupt 0 has the highest priority• Among the vectored interrupts, the higher numbered vectored interrupt has lower priority• Within the VIC, all default-vectored interrupts have the same priority, which is thelowest priority.