Sharp Blue Treak LH75400 User Manual

UART0 and UART1 LH75400/01/10/11 (Preliminary) User’s Guide19-16 7/15/03Table 19-17. LCTRL_H Register DefinitionsBIT NAME DESCRIPTION31:8 /// Reserved Read as zero.7 STICK PARITYSELECTStick Parity Select Bits [7], [2], and [1] work together to set up theparity. See Table 19-18.6:5 WORD LENGTHWord Length Indicates the number of data bits transmitted orreceived in a frame.00 = 5 bits01 = 6 bits10 = 7 bits11 = 8 bits4 ENABLE FIFOSFIFO Enable Buffers1 = Enables transmit and receive FIFO buffers (FIFO Mode). Whencleared to 0, the FIFOs are disabled (Character Mode); that is,the FIFOs become 1-byte-deep holding registers.3 TWO STOP BITSSELECTFrame Stop Bits1 = Two stop bits are transmitted at the end of the frame. Thereceive logic always checks for received stop bits, regardlessof whether there are one or two.2 EVEN PARITYSELECTEven Parity Select Bits [7], [2], and [1] work together to set up theparity. See Table 19-18.1 PARITY ENABLE Parity Enable Bits [7], [2], and [1] work together to set up theparity. See Table 19-18.0 SEND BREAK1 = A LOW level is continuously output on the UARTTXD output,after completing transmission of the current character. This bitmust be asserted for at least one complete frame transmissiontime to generate a break condition. The transmit FIFO contentsremain unaffected during a break condition. For normal use,this bit must be cleared to zero.Table 19-18. Truth Table for bits [7], [2], and [1]PARITYENABLE (PEN)EVEN PARITYSELECT (EPS)STICK PARITYSELECT (SPS)RESULTANT PARITY BIT(TRANSMITTED OR CHECKED)0 X X Not transmitted or checked1 1 0 Even parity1 0 0 Odd parity1 0 1 11 1 1 0