LH75400/01/10/11 (Preliminary) User’s Guide Color Liquid Crystal Display Controller7/15/03 13-31Figure 13-2. STN Horizontal Timing Diagram1 STN HORIZONTAL LINECLCDC CLOCK(INTERNAL)APBPeriphClkCtrl1:LCDClkPrescale:LCDPSLCDLP(LINESYNCHRONIZATIONPULSE)Timing2:IHSLCDDCLK(PANEL CLOCK)Timing2:PCDTiming2:BCDTiming2:IPCTiming2:CPLLCDVD[11:0](PANEL DATA)THE ACTIVE DATA LINESWILL VARY WITH THETYPE OF STN PANEL:4-BIT, 8-BIT, COLOR,OR MONONOTES:1. The CLCDC clock (from the RCPC) is scaled within the CLCDC and used to produce the LCDDCLKoutput. CLCDC registers set timing (in terms of LCDDCLK pulses) to produce the other signals thatcontrol an STN display.2. The duration ot the LCDLP signal is controlled by Timing0:HSW (the HSW bit field in the Timing0 Register).3. The polarity of the LCDLP signal is set by Timing2:IHS.Timing0:HSWTiming0:HBP Timing0:PPLD001 D002 D....ONE 'LINE' OF LCD DATADNNNTiming0:HFPHORIZONTALBACK PORCHHORIZONTALFRONT PORCHENUMERATEDIN 'LCDDCLKS'ENUMERATEDIN 'LCDDCLKS'LH754xx-77LCDDCLK ISSUPPRESSEDDURING LCDLP