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LH79524
Sharp LH79524 User Manual
Sharp LH79524 User Manual
Table of content
Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Overview
Version
Table 1-1. LH79524/LH79525 Differences
Figure 1-1. LH79524/LH79525 Block Diagram
Table 1-2. Clock Descriptions
Figure 1-2. Standard Clocking Modes
Figure 1-3. Fastbus Clocking Mode
Table 1-3. Port C Settings For Boot
Figure 1-4. Reset Circuit for TAP Controller
Hardware Requirements at Reset
Active Pull Ups
AHB Bus Master Priority and Arbitration
Table 1-5. AHB Memory Mapping
Table 1-8. Internal SRAM Memory Section Mapping
Table 1-11. Primary AHB Peripheral Register Mapping
Table 1-12. APB Peripheral Register Mapping
Instruction and Data Cache
Theory of Operation
Figure 2-1. ADC Block Diagram
Bias-and-Control Network
Figure 2-2. Bias-and-Control Network Block Diagram
Clock Generator
Figure 2-4. Example of a 4-bit SAR ADC Operation
Battery Control Feature
Timing Formulas
Pen Interrupt
Register Reference
Register Descriptions
Table 2-4. In + Mux Definition
Low Word Register (LW)
Results Register (RR)
Interrupt Mask Register (IM)
Power Configuration Register (PC)
Table 2-13. Touch Screen Controller Power Modes
General Configuration Register (GC)
General Status Register (GS)
Interrupt Status Register (IS)
FIFO Status Register (FS)
Control Bank Registers
Idle High Word Register (IHWCTRL)
Idle Low Word Register (ILWCTRL)
Masked Interrupt Status Register (MIS)
Interrupt Clear Register (IC)
Figure 3-1. Boot Controller Block Diagram
Table 3-1. Boot Configuration for Silicon Version A.0
NAND Flash Operation
NAND Flash Hardware Design
Table 3-5. Supported Devices
Booting from UART
Register Definitions
nCS1 Override Register (CS1OV)
External Peripheral Mapping Register (EPM)
Introduction
LCD Panel Architecture
CLCDC Features
Figure 4-3. Color LCD Controller Block Diagram
Supported Displays and Panels
Pixel Serializer
Table 4-3. Frame Buffer Pixel Storage Format [15:0]
Palette RAM
Grayscale Algorithm
Table 4-6. Supported TFT, HR-TFT, and AD-TFT LCD Panels
Table 4-9. Color STN Intensities From Gray-Scale Modulation
LCD Data Multiplexing
LCD Interface Timing Signals
LCD Vertical Timing Signals
LCD Power Sequencing at Turn-On and Turn-Off
Minimizing a Retained Image on the LCD
Advanced LCD Interface
ALI Theory of Operation
CLCDC Register Reference
CLCDC Register Descriptions
Vertical Timing Panel Control Register (TIMING1)
Clock and Signal Polarity Control Register (TIMING2)
Upper Panel Frame Buffer Base Address Register (UPBASE)
Lower Panel Frame Buffer Base Address Register (LPBASE)
Interrupt Enable Register (INTREN)
CLCDC Control Register (CTRL)
Table 4-27. CTRL Fields
Raw Interrupt Status Register (STATUS)
Masked Interrupt Status Register (INTERRUPT)
Interrupt Clear Register (INTCLR)
LCD Upper Panel and Lower Panel Frame Buffer Current Address Register (UPCURR and LPCURR)
bit Color Palette Register (PALETTE)
Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC)
ALI Register Reference
Control Register (ALICTRL)
Timing Delay Register 1 (ALITIMING1)
Timing Delay Register 2 (ALITIMING2)
STN Horizontal Timing
Figure 4-6. STN Horizontal Timing Diagram
Figure 4-7. STN Vertical Timing Diagram
Figure 4-8. TFT Horizontal Timing Diagram
Figure 4-9. TFT Vertical Timing Diagram
Figure 4-10. AD-TFT, HR-TFT Horizontal Timing Diagram
Table 5-1. DMA Controller Stream Assignments and Request Priority
Use for SSP and UART
Interrupt, Error, and Status Registers
Memory Map
Destination Base Registers (DESTLO and DESTHI)
Maximum Count Register (MAX)
Control Register (CTRL)
Table 5-16. DMA Data Width
Table 5-18. Constraints on CTRL Field Values Based on Stream Type
Current Source Registers (CURSHI and CURSLO)
Current Destination Registers (CURDHI and CURDLO)
Terminal Count Register (TCNT)
Interrupt Mask Register (MASK)
Interrupt Clear Register (CLR)
Status Register (STATUS)
Operational Overview
Setup
Table 6-1. Receive Buffer Descriptor LIst
Transmit Buffer
Receive Block
Pause Frame Support
Address Checking Block
Broadcast Address
Type ID Checking
Initialization
Figure 6-2. Address Matching
Transmit Buffer List
PHY Maintenance
Control, Configuration, And Status Register Definitions
Network Configuration Register (NETCONFIG)
Network Status Register (NETSTATUS)
Transmit Status Register (TXSTATUS)
Receive Buffer Queue Pointer (RXBQP)
Transmit Buffer Queue Pointer (TXBQP)
Receive Status Register (RXSTATUS)
Interrupt Status Register (INSTATUS)
Interrupt Enable Register (ENABLE)
Interrupt Disable Register (DISABLE)
PHY Maintenance Register (PHYMAINT)
Pause Time Register (PAUSETIME)
Statistics Register Definitions
Frames Transmitted OK (FRMTXOK)
Multiple Collision Frames (MULTFRM)
Frame Check Sequence Errors (FRCHK)
Deferred Transmission Frames (DEFTXFRM)
Excessive Collisions (EXCOL)
Carrier Sense Errors (SENSERR)
Receive Resource Errors (RXRERR)
Receive Symbol Errors (RXSYMERR)
Receive Jabbers (RXJAB)
SQE Test Errors (SQERR)
Transmitted Pause Frames (TXPAUSEFM)
Matching Registers
Specific Address 1 Bottom (SPECAD1BOT)
Specific Address 2 Bottom (SPECAD2BOT)
Specific Address 3 Bottom (SPECAD3BOT)
Specific Address 4 Bottom (SPECAD4BOT)
Type ID Checking (IDCHK)
Figure 7-1. External Memory Controller Block Diagram
External Memory Map
Figure 7-2. Automatic Address Shifting
Hardware Design
Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices
Figure 7-7. 32-bit Memory Bank Constructed From a Single 32-bit Device
Figure 7-8. Typical Memory Connection Diagram
Software Design
Static Memory Device Selection
Figure 7-10. Static Read Transaction with Zero Wait States
Figure 7-11. Static Read Transaction with Three Wait States
Figure 7-12. Static Write Transaction with Zero Wait States
Figure 7-13. Static Write Transaction with Two Wait States
Bus Turnaround
Extended Wait Transfers
Table 7-2. Boot Configuration for Silicon Version A.0
Figure 7-14. Connection to NAND Flash
General NAND Flash Access
bit Example Transaction
Dynamic Memory
Table 7-6. 32-bit Wide Data Bus Address Mapping, SDRAM (BRC)
Table 7-7. 16-bit Wide Data Bus Address Mapping, SDRAM (RBC)
Table 7-8. 16-bit Wide Data Bus Address Mapping, SDRAM (BRC)
Data Mask Signals
Configuration Register (CONFIG)
Dynamic Memory Control Register (DYNMCTRL)
Dynamic Refresh Register (DYNMREF)
Dynamic Memory Read Configuration Register (DYNMRCON)
Dynamic Precharge Command Period Register (PRECHARGE)
Dynamic Memory Active to Precharge Command Period Register (DYNM2PRE)
Dynamic Memory Self-Refresh Exit Time Register (REFEXIT)
Dynamic Memory Last Data Out to Active Time Register (DOACTIVE)
Dynamic Memory Data-In to Active Time Register (DIACTIVE)
Dynamic Memory Write Recovery Time Register (DWRT)
Dynamic Memory Active to Active Command Period Register (DYNACTCMD)
Dynamic Memory Auto-Refresh Period, and Auto-Refresh to Active Command Period Register (DYNAUTO)
Dynamic Memory Exit Self-Refresh to Active Command Time Register (DYNREFEXIT)
Dynamic Memory Active Bank A to Active Bank B Time Register (DYNACTIVEAB)
Dynamic Memory Load Mode Register to Active Command Time Register (DYNAMICTMRD)
Static Memory Extended Wait Register (WAIT)
Dynamic Configuration Register for nDCS0 and nDCS1 (DYNCFGx)
Table 7-49. Address Mapping
Dynamic Memory RAS and CAS Delay Register for nDCS0 and nDCS1 (DYNRASCASx)
Static Memory Configuration Register (SCONFIGx)
Static Memory Write Enable Delay Registers (SWAITWENx)
Static Memory Output Enable Delay Registers (SWAITOENx)
Static Memory Read Delay Registers (SWAITRDx)
Table 7-60. SWAITPAGEx Register
Static Memory Write Delay Registers (SWAITWRx)
Static Memory Turn Around Delay Registers (STURNx)
Multiplexing
Table 8-3. LH79525 GPIO Multiplexing
Port B/D/F/H/J/L/N Data Register (P2DRx)
Port A/C/E/G/I/K Data Direction Register (P1DDRx)
Port B/D/F/H/L/N Data Direction Register
Interrupt Handling
Slave Mode
Table 9-6. ICSAR Register
Table 9-8. ICUSAR Register
Table 9-12. ICHCNT Register
Table 9-16. ICSTAT Register
Driving/Latching Edges
Transmission
Slave Mode Transmission
Reception
Slave Mode Reception
Suppression of SSPFSSIN
Interrupts
Receive Interrupt
Table 10-4. WSINV Functionality
Status Register (STAT)
Interrupt Mask Set or Clear Register (IMSC)
Raw Interrupt Status Register (RIS)
Interrupt Clear Register (ICR)
Resistor Configuration Control 1 Register (RESCTL1)
Multiplexing Control 3 Register (MUXCTL3)
Multiplexing Control 4 Register (MUXCTL4)
Resistor Configuration Control 4 Register (RESCTL4)
Multiplexing Control 5 Register (MUXCTL5)
Resistor Configuration Control 5 Register (RESCTL5)
Multiplexing Control 6 Register (MUXCTL6)
Resistor Configuration Control 6 Register (RESCTL6)
Multiplexing Control 7 Register (MUXCTL7)
Resistor Configuration Control 7 Register (RESCTL7)
Multiplexing Control 10 Register (MUXCTL10)
Resistor Configuration Control 10 Register (RESCTL10)
Multiplexing Control 11 Register (MUXCTL11)
Resistor Configuration Control 11 Register (RESCTL11)
Multiplexing Control 12 Register (MUXCTL12)
Resistor Configuration Control 12 Register (RESCTL12)
Resistor Configuration Control 13 Register (RESCTL13)
Multiplexing Control 14 Register (MUXCTL14)
Multiplexing Control 15 Register (MUXCTL15)
Resistor Configuration Control 17 Register (RESCTL17)
Multiplexing Control 19 Register (MUXCTL19)
Resistor Configuration Control 19 Register (RESCTL19)
Multiplexing Control 20 Register (MUXCTL20)
Resistor Configuration Control 20 Register (RESCTL20)
Multiplexing Control 21 Register (MUXCTL21)
Resistor Configuration Control 21 Register (RESCTL21)
Multiplexing Control 22 Register (MUXCTL22)
Resistor Configuration Control 22 Register (RESCTL22)
Multiplexing Control 23 Register (MUXCTL23)
Resistor Configuration Control 23 Register (RESCTL23)
Multiplexing Control 24 Register (MUXCTL24)
Resistor Configuration Control 24 Register (RESCTL24)
Multiplexing Control 25 Register (MUXCTL25)
Configuring the RTC for Use
Match Register (MR)
Control Register (CR)
System PLL and USB PLL Reset
Peripheral Block Clocks
Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies
Power Modes
Stop2 Mode
Identification Register (CHIPID)
Remap Control Register (REMAP)
Figure 13-4. Remap = 0b01
Figure 13-6. Remap = 0b11
Software Reset Register (SOFTRESET)
Reset Status Register (RSTSTATUS)
Reset Status Clear Register (RSTSTATUSCLR)
System Clock Prescaler Register (SYSCLKPRE)
CPU Clock Prescaler Register (CPUCLKPRE)
Peripheral Clock Control Register 0 (PCLKCTRL0)
Peripheral Clock Control Register 1 (PCLKCTRL1)
AHB Clock Control Register (AHBCLKCTRL)
Peripheral Clock Select Register 0 (PCLKSEL0)
Peripheral Clock Select Register 1 (PCLKSEL1)
Silicon Revision Register (SILICONREV)
LCD Clock Prescaler Register (LCDPRE)
SSP Clock Prescaler Register (SSPPRE)
ADC Clock Prescaler Register (ADCPRE)
USB Clock Prescaler Register (USBPRE)
External Interrupt Configuration Register (INTCONFIG)
External Interrupt Clear Register (INTCLR)
Core Clock Configuration Register (CORECONFIG)
System PLL Control Register (SYSPLLCTL)
USB PLL Control Register (USBPLLCTL)
Table 14-1. Feature Comparison
Timing Waveforms
Motorola SPI Frame Format
Texas Instruments Frame Format
National Semiconductor Frame Format
Clock Generation
Transmit Interrupt
Control Register 1 (CTRL1)
Data Register – Receive/Transmit FIFO Register (DR)
Status Register (SR)
Clock Prescale Register (CPSR)
Interrupt Mask Set and Clear Register (IMSC)
DMA Control Register (DCR)
Counter Clear Upon Compare Match
Capture Signal Sampling
Timer Interrupts
Timer 0 Compare/Capture Control Register (CMP_CAP_CTRL0)
Timer 0 Interrupt Control Register (INTEN0)
Timer 0 Status Register (STATUS0)
Timer 0 Counter Register (CNT0)
Timer 0 Compare Registers (T0CMPn)
Timer 0 Capture Registers (CAPn)
Timer 1 Control Register (CTRL1)
Timer 1 Interrupt Control Register (INTEN1)
Timer 1 Status Register (STATUS1)
Timer 1 Counter Register (CNT1)
Timer 1 Compare Registers (T1CMPn)
Timer 1 Capture Registers (T1CAPn)
Timer 2 Control Register (CTRL2)
Timer 2 Interrupt Control Register (INTEN2)
Timer 2 Status Register (STATUS2)
Timer 2 Counter Register (CNT2)
Timer 2 Compare Registers (T2CMPn)
Timer 2 Capture Registers (T2CAPn)
Transmitting Data
Nine-bit Mode
On-Chip DMA Capabilities
Hardware Flow Control
Receive Status/Error Clear Register (UARTRSR/UARTECR)
Table 16-8. UARTRSR/UARTECR Register (Read Operations)
Flag Register (UARTFR)
IrDA Low-Power Counter Register (UARTILPR)
Integer Baud Rate Divisor Register (UARTIBRD)
Fractional Baud Rate Divisor Register (UARTFBRD)
Line Control Register (UARTLCR_H)
Table 16-21. Truth Table for 9BIT, SPS, EPS, and PEN bits
UART Control Register (UARTCR)
Interrupt FIFO Level Select Register (UARTIFLS)
Interrupt Mask Set/Clear Register (UARTIMSC)
Raw Interrupt Status Register (UARTRIS)
Masked Interrupt Status Register (UARTMIS)
Interrupt Clear Register (UARTICR)
UART0 DMA Control Register (DMACTRL)
Endpoints
Isochronous Endpoints
DMA Interface
DMA Operation
DMA Mode 1: OUT Endpoints
DMA Mode 1: IN Endpoints
Power Management Register (PMR)
Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR)
Interrupt Register for OUT Endpoint 1 and 2 (OIR)
Interrupt Register for common USB interrupts (UIR)
IN Interrupt Enable Register (IIE)
OUT Interrupt Enable Register (OIE)
Interrupt Enable Register (UIE)
Frame Number Registers (FRAMEx)
Indexed Registers
IN Maximum Packet Size Register (INMAXP)
Control Status Register for EP 0 (CSR0)
Control Status Register 1 for IN EP 1, 2, and 3 (INCSR1)
Control Status Register 2 for IN EP 1, 2, and 3 (INCSR2)
OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP)
Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR1)
Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2)
Count 0 Register (OUTCOUNT0)
Out Count 2 Register (OUTCOUNT2)
Pending DMA Interrupts Register (INTR)
DMA Channel x Control Register (CNTLx)
DMA Channel x AHB Memory Address Register
VIC Interrupt Listing
Vectored Interrupts
Clearing Interrupts
FIQ Status Register (FIQSTATUS)
Interrupt Select Register (INTSELECT)
Interrupt Enable Clear Register (INTENCLEAR)
Software Interrupt Register (SOFTINT)
Software Interrupt Clear Register (SOFTINTCLEAR)
Vector Address Register (VECTADDR)
Vector Address Registers (VECTADDRx)
Vector Control Registers (VECTCTRLx)
Interrupt Test Output Register (ITOP)
Figure 19-1. Watchdog Timer Block Diagram
WDT Operation Details
Counter Reset Register (RST)
Current Watchdog Count Registers (COUNT[3:0])
LH79524/LH79525
User’s Guide
Version 1.0
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This manual is suitable for:
LH79524
LH79525
