Toshiba TC9349AFG Manual

TC9349AFG2006-02-2442{ Register portThe G-register, data register and DAL address register, which were mentioned in the description of the CPU, are arrangedon the I/O map, and treated as one of the internal ports. The carry flag can also be accessed from an I/O map. (Refer to thesection on I/O access of the stack register.)Of these registers, the G-register, the carry flag, and the data register have a four-page interrupt stack registercorresponding to the four stack levels. On execution of interrupt processing, these contents are automatically stored in theinterrupt stack register together with the contents of data selection and automatically returned on execution of an RNIinstruction. (Refer to the section on the interrupt stack register.)1. G-register (φL/K18, φL/K19)This register addresses the row addresses (DR = 04H ~ 1FH) of the data memory during execution of the MVGDinstruction and MVGS instruction. The register is accessed with the OUT1/IN1 instruction for which [CN = 8H ~ 9H] hasbeen specified in the operand. Moreover, if the STGI instruction is used, data can be set to this register with a singleinstruction.This register has a four-level interrupt stack register. On the issuing of interrupt, the contents of the G-register areevacuated to the interrupt register specified by the interrupt stack pointer and returned by the RNI instruction.Note: The contents of this register are only valid when the MVGD instruction and MVGS instruction areexecuted and are ineffective when any other instruction is executed. Moreover, this register is unaffectedby the MVGD instruction and MVGS instruction.Note: All of the data memory row addresses can be specified indirectly by setting data 00H to 1FH in the G-register (DR = 00H ~ 1FH).Note: It is possible to rewrite and reference the contents of the interrupt stack registers ISRG0 ~ ISRG4(φL/K10(8), φL/K10(9)) through programming.φL/K18Y1 Y2 Y4 Y8φL/K19 G4Y1 Y2 Y4 Y8* * *STGI instructionG-registerＩ0 Ｉ1 Ｉ2 Ｉ3 Ｉ4Ｉ*G4 G3 G2 G1 G00 0 0 010 0 010 0 01111111 1DR04H05H06H1FHφL/K10(6)Y1 Y2 Y4 Y8*/0 */0ISP1ISP0Interruption stack pointerG0 G1 G2 G3ISRG0 ISRG1 ISRG2 ISRG30123At the time of interruptionprocessing executionAt the time of RNIinstruction executionφL/K10(8)ISRG4 */0 */0 */00123φL/K10(9)～～～～Interruption stack registerPage PageSpecification of the low address of a data memoryInterrupt stack pointerAt the time of interruptprocessing executionInterrupt stack pointerAt the time of interruptprocessing executionInterrupt stack register