Toshiba TC9349AFG Manual

TC9349AFG2006-02-2431{ DC/DC converter for CPUThe device incorporates a DC/DC converter for the CPU power supply. The CPU doubler circuit comprises a chargepump system utilizing a capacitor.There is a built-in clamp control function, for which an electrical potential of 2.0, 2.5 and 3.0 V can be set throughprogramming.The capacitor-utilizing charge pump system supplies a VDD level charge between the C1 and C2 pins, and a doublerpotential twice the VDD potential is output to the VDB pin. Note that, if twice the voltage of the VDD pin decreasesfollowing clamp setting using this method, the doubler potential also decreases.Three types of 1/2 frequency can be selected for the doubler clock: 37.5 kHz, 75 kHz, and a high-speed oscillation clock.After reset, a frequency of 37.5 kHz is output. Set the doubler clock to the required doubler capability.The doubled VDB potential is supplied to the A/D converter and the VEE constant-voltage circuit. The VDB potential isusually supplied to the VCPU pin through a Schottky diode.Note: If the OSC2 bit is set to “1”, the doubler clock for the LCD driver is also changed simultaneously.OSC2 ON(φL15(F)-Y2) OSC2 Doubler Clock Frequency for the CPUDoubler ClockFrequency forthe LCD Driver* 0 Low-speed oscillator clock (75kHz)×1/2 Same as left0 1 Low-speed oscillator clock (75kHz)1 1 High-speed oscillator clock (300～600kHz)×1/2Low-speedoscillator clockVC0 VC1 Clamp voltage0 0 Prohibition0 1 2.0V1 0 2.5V1 1 3.0V0: Off（VDD × 2）1: OnClamp function controlDoubler clock frequency selection for doublerY1 Y2 Y4 Y8φL14(8) VC0 VC1 CLAMP OSC2Clamp voltage controlNote: This becomes effective only when the clamp function is ON.