Toshiba TC9349AFG Manual

TC9349AFG2006-02-241014. Programmable Counter Circuit ConfigurationThe circuit consists of an amplifier, 1/15･16 2-modulus pre-scaler, a 4-bit swallow counter and a 12-bit binaryprogrammable counter. When the HF mode is selected, the 1/15･16 pre-scaler, the 4-bit swallow counter and the 12-bitbinary programmable counter are used. When the LF mode is selected, only the 12-bit binary programmable counter isused.The OSCin input clock is supplied to the DC-DC converter for VT, and used as the doubler clock. The clock dividedby the programmable counter is also supplied to the phase comparator and the IF counter.(→ Refer to the sections on DC-DC converter for VT and Phase comparator.)Note: The programmable counter uses the V PLL pin power supply. This power supply can be suppliedregardless of the power supply level of the V DD/VCPU pin. In the PLL off mode, the V PLL pin powersupply can be turned off. The programmable counter setting registers use the V CPU pin power supply, sothat the contents of the registers are retained after the VPLL pin power supply is turned off.Note: The OSCin pin has an amplifier that allows small-amplitude operation with coupled capacitor. The OSCininput is subject to high impedance in the PLL off mode.51OSCin0.01 μFAmplifier 1/161/151/15･164-bitswallow counter12-bitprogrammable counterP4~P15P0~P3PresetTA0, TA1To phase comparator50VPLLLFHFHFTo DC-DC converter for VT To phase comparatorTo IF counter