Xilinx M401 User Manual

Xilinx M401 User Manual Manual pdf 27 page image

ML401/ML402/ML403 Evaluation Platform www.xilinx.com 27UG080 (v2.5) May 24, 2006Detailed DescriptionR19. Linear Flash ChipsTwo 32-Mb linear flash devices (Micron MT28F320J3RG-11 ET) are installed on the boardfor a total of 8 MB of flash memory. These flash memory chips are Intel StrataFlashcompatible. This memory provides non-volatile storage of data, software, or bitstreams.Each flash chip is 16 bits wide and together forms a 32-bit data bus that is shared withSRAM. In conjunction with a CPLD, the flash memory can also be used to program theFPGA.Note: The reset for the AC97 Codec is shared with the reset signal for the flash memory chips andis designed to be asserted at power-on or upon system reset.20. Xilinx XC95144XL CPLDA Xilinx XC95144XL CPLD is connected to the flash memory and the FPGA configurationsignals. This CPLD connection supports applications where flash memory programs theFPGA. The CPLD is programmed from the main JTAG chain of the board. The CPLD iswired so that it can support master or slave configuration in serial or parallel (SelectMAP)modes. For FPGA configuration via the CPLD and flash, the configuration selector switch(SW12) must be set to the CPLD Flash position. See the “Configuration Options,” page 31section for more information.21. 10/100/1000 Tri-Speed Ethernet PHYThe ML40x evaluation platform contains a Marvell Alaska PHY device (88E1111) operatingat 10/100/1000 Mb/s. The board supports MII, GMII, and RGMII interface modes with theFPGA. The PHY is connected to a Halo HFJ11-1G01E RJ-45 connector with built-inmagnetics. A 25-MHz crystal supplies the clock signal to the PHY. The PHY is configuredto default at power-on or reset to the following settings (See Table 14). These settings maybe overwritten via software.Table 14: Board Connections for PHY Configuration PinsConfig Pin Connection onBoardBit[2] Definition andValueBit[1] Definition andValue Bit[0] Definition and ValueCONFIG0 Ground PHYADR[2] = 0 PHYADR[1] = 0 PHYADR[0] = 0CONFIG1 Ground ENA_PAUSE = 0 PHYADR[4] = 0 PHYADR[3] = 0CONFIG2 V CC 2.5V ANEG[3] = 1 ANEG[2] = 1 ANEG[1] = 1CONFIG3 VCC 2.5V ANEG[0] = 1 ENA_XC = 1 DIS_125 = 1CONFIG4 VCC 2.5V HWCFG_MODE[2] = 1 HWCFG_MODE[1] = 1 HWCFG_MODE[0] = 1CONFIG5 VCC 2.5V DIS_FC = 1 DIS_SLEEP = 1 HWCFG_MODE[3] = 1CONFIG6 LED_RX SEL_BDT = 0 INT_POL = 1 75/50Ω = 0www.BDTIC.com/XILINX