Xilinx M401 User Manual

Xilinx M401 User Manual Manual pdf 17 page image

ML401/ML402/ML403 Evaluation Platform www.xilinx.com 17UG080 (v2.5) May 24, 2006Detailed DescriptionR4. Oscillator SocketsThe ML40x evaluation platform has two crystal oscillator sockets, each wired for standardLVTTL-type oscillators. (A 100-MHz oscillator is pre-installed in the X1 SYSCLK socket.)These connect to the FPGA clock pins as shown in Table 4. The oscillator sockets accepthalf-sized oscillators and are powered by the 3.3V supply.5. LCD Brightness and Contrast AdjustmentTurning potentiometer R1 adjusts the image contrast of the character LCD.6. DIP Switches (Active-High)Eight general purpose (active-High) DIP switches are connected to the user I/O pins of theFPGA. Table 5 summarizes these connections.Note: On the ML403 board, these DIP switches are not installed.Table 4: Oscillator Socket ConnectionsLabel Clock Name FPGA PinX1 SYSCLK AE14X6 USERCLK AD12Table 5: DIP Switches Connections (SW1)SW1 FPGA Pin1 R202 R193 T264 U265 U236 V237 U258 U24www.BDTIC.com/XILINX