Xilinx M401 User Manual

Xilinx M401 User Manual Manual pdf 25 page image

ML401/ML402/ML403 Evaluation Platform www.xilinx.com 25UG080 (v2.5) May 24, 2006Detailed DescriptionR14. IIC Bus with 4-Kb EEPROMAn IIC EEPROM (Microchip Technology 24LC04B-I/ST) is provided on the ML40x boardto store non-volatile data such as an Ethernet MAC address. The EEPROM write protect istied off on the board to disable its hardware write protect. The IIC bus uses 2.5V signalingand can operate at up to 400 kHz. IIC bus pull-up resistors are provided on the board.The IIC bus is extended to the expansion connector so that the user may add additional IICdevices and share the IIC controller in the FPGA. If the expansion IIC bus is to be utilized,the user must have additional IIC pull-up resistors present on the expansion card.Bidirectional level shifting transistors allow the expansion card to utilize 2.5V to 5Vsignaling on IIC.15. VGA OutputThe VGA output port (P2) supports an external video monitor. Table 13 lists each boardand its corresponding video DAC chip.Note: Due to the reduced pin count on ML403 board’s XC4VFX12 FPGA, only the five mostsignificant bits of digital RGB data are connected to the video DAC. The three least significant bits ofdigital RGB data are pulled Low.16. PS/2 Mouse and Keyboard PortsThe ML40x evaluation platform contains two PS/2 ports: one for a mouse (J17) and theother for a keyboard (J18). Bidirectional level shifting transistors allow the FPGA's2.5V I/O to interface with the 5V I/O of the PS/2 ports. The PS/2 ports on the board arepowered directly by the main 5V power jack, which also powers the rest of the board.Caution! Care must be taken to ensure that the power load of any attached PS/2 devices doesnot overload the AC adapter.Table 13: Video DAC ConnectionsBoard Speed Description Video MonitorML401 50 MHz 24-bit video data busconnected to FPGAAnalog Devices ADV7125KST50ML402140 MHz Analog Devices ADV7125KST140ML403 15-bit video data busconnected to FPGAwww.BDTIC.com/XILINX