Xilinx M401 User Manual

Xilinx M401 User Manual Manual pdf 14 page image

14 www.xilinx.com ML401/ML402/ML403 Evaluation PlatformUG080 (v2.5) May 24, 2006Detailed Description R1. Virtex-4 FPGAA Xilinx Virtex-4 FPGA is installed on the evaluation platform (the board):♦ ML401: XC4VLX25-FF668-10♦ ML402: XC4VSX35-FF668-10♦ ML403: XC4VFX12-FF668-10ConfigurationThe board supports configuration in all modes: JTAG, Master Serial, Slave Serial, MasterSelectMAP, and Slave SelectMAP modes. See the “Configuration Options,” page 31 sectionfor more information.I/O Voltage RailsThe FPGA has 11 banks of which only the first 10 banks are used. The last bank is poweredbut unused. The I/O voltage applied to each bank is summarized in Table 1.Table 1: I/O Voltage Rail of FPGA BanksFPGA Bank I/O Voltage Rail0 3.3V1 3.3V2 3.3V3 2.5V4 3.3V5 2.5V6 2.5V7 User selectable as 2.5V or 3.3V using jumper J168 3.3V9 aa. Bank 9 and 10 are non-connected pins in the case of the ML403 with XC4VFX12-FF668.3.3V10 a 3.3V (Powered but I/O pins are not used)www.BDTIC.com/XILINX