Xilinx M401 User Manual

Xilinx M401 User Manual Manual pdf 16 page image

16 www.xilinx.com ML401/ML402/ML403 Evaluation PlatformUG080 (v2.5) May 24, 2006Detailed Description R2. DDR SDRAMThe board contains 64 MB of DDR SDRAM using two Infineon HYB25D256160BT-7 (orcompatible) chips (U4 and U5). Each chip is 16 bits wide and together form a 32-bit databus capable of running up to 266 MHz. All DDR SDRAM signals are terminated through47Ω resistors to a 1.25V VTT reference voltage. The board is designed for matched lengthtraces across all DDR control and data signals except clocks and the DDR Loop trace (see“DDR Clock Signal” and “DDR Loop Signal”).The board can support up to 256 MB of total DDR SDRAM memory if larger chips areinstalled. An extra address pin is present on the board to support up to 1-Gb DDR chips.DDR Clock SignalThe DDR clock signal is broadcast from the FPGA as a single differential pair that drivesboth DDR chips. The delay on the clock trace is designed to match the delay of the otherDDR control and data signals. The DDR clock is also fed back to the FPGA to allow forclock deskew using Virtex-4 DCMs. The board is designed so that the DDR clock signalreaches the FPGA clock feedback pin at the same time as it arrives at the DDR chips.DDR Loop SignalThe DDR loop signal is a trace driven and then received back at the FPGA with a delayequal to the sum of the trace delays of the clock and DQS signals. This looped trace can beused in high-speed memory controllers to help compensate for the physical trace delaysbetween the FPGA and DDR chips.3. Differential Clock Input And Output With SMA ConnectorsHigh-precision clock signals can be input to the FPGA using differential clock signalsbrought in through 50Ω SMA connectors. This allows an external function generator orother clock source to drive the differential clock inputs that directly feed the global clockinput pins of the FPGA. The FPGA can be configured to present a 100Ω terminationimpedance.A differential clock output from the FPGA is driven out through a second pair of SMAconnectors. This allows the FPGA to drive a precision clock to an external device such as apiece of test equipment. Table 3 summarizes the differential SMA clock pin connections.Table 3: Differential SMA Clock ConnectionsLabel Clock Name FPGA PinJ10 SMA_DIFF_CLK_IN_N C12J7 SMA_DIFF_CLK_IN_P C13J8 SMA_DIFF_CLK_OUT_N D7J9 SMA_DIFF_CLK_OUT_P D8www.BDTIC.com/XILINX