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Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 675UG586 November 30, 2016 www.xilinx.comAppendix A: General Memory Routing Guidelines13. To optimize the signal routing, the recommendation for one component placement isshown in Figure A-7.X-Ref Target - Figure A-7Figure A-7: Component Placement Recommendations for One ComponentV 55RESETA13VDDA7A9V55A5A1VAEDQV000DQ4VA55QDQ6LDQ5#VDDQDQ2LDQ5V55V55QDQ0V550DQQUDMVD0QDQ11DQ9V550VDDV55V000DQ13DQ15VDDA3A0V55BA0BA2NCCS#WE#ODTVDDCAS#NICV55RAS#A14A8V 55A11A6V00A1A4V 55DQ7DQ5V00QVDDV 55V 55QVDDQV 55QV 00 QLDMV 55QDQ0DQ8V 55QV00UDQSDQ10V000UDQS#DQ14V 55QDQ12V 00QV 555A12BC#BA1V00NCV REFCAV 55A10APZQNCCK#V DDCKECKV 55NCcmd/addr/ctrlFPGAcmd/addr/ctrl routing channel dq routing channeldqUG583_c2_18_073014Send Feedback |
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