Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 670UG586 November 30, 2016 www.xilinx.comAppendix A: General Memory Routing Guidelines6. Signal lines must be routed over a solid reference plane. Avoid routing over voids(Figure A-2).X-Ref Target - Figure A-2Figure A-2: Signal Routing Over Solid Reference PlaneUG583_c2_13_050614Send Feedback

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Appendix A: General Memory Routing Guidelines

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