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Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Contents
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 351UG586 November 30, 2016 www.xilinx.comChapter 2: QDR II+ Memory Interface SolutionThe sys_clk can be input on any CCIO in the column where the memory interfaces arelocated. This includes CCIO in banks that do not contain the memory interfaces, butmust be in the same column as the memory interfaces.Information on Sharing BUFG Clock (phy_clk)The MIG 7 series QDR II+ SRAM design includes an MMCM which outputs the phy_clk ona BUFG route. It is not possible to share this clock amongst multiple controllers tosynchronize the user interfaces. This is not allowed because the timing from the FPGA logicto the PHY Control block must be controlled. This is not possible when the clock is sharedamongst multiple controllers. The only option for synchronizing user interfaces amongstmultiple controllers is to create an asynchronous FIFO for clock domain transfer.Information on Sync_PulseThe MIG 7 series QDR II+ SRAM design includes one PLL that generates the necessarydesign clocks. One of these outputs is the sync_pulse. The sync pulse clock is 1/16 of themem_refclk frequency and must have a duty cycle distortion of 1/16 or 6.25%. This clockis distributed across the low skew clock backbone and keeps all PHASER_IN/_OUT andPHY_Control blocks in sync with each other. The signal is sampled by the mem_refclk inboth the PHASER_INs/_OUTs and PHY_Control blocks. The phase, frequency, and duty cycleof the sync_pulse is chosen to provide the greatest setup and hold margin across PVT.Debugging QDR II+ SRAM DesignsThis section defines a step-by-step debugging procedure to assist in the identification andresolution of any issues that might arise during each phase of the memory interface designprocess.Note: The overall read latency of the MIG 7 series QDR II+ core is dependent on how the MemoryController is configured, but most critically on the target traffic/access pattern and the number ofcommands already in the pipeline before the read command is issued. Read latency is measured fromthe point where the read command is accepted by the user or native interface. Simulation should berun to analyze read latency.IntroductionThe QDR II+ memory interfaces in Virtex-7 FPGAs simplify the challenges associated withmemory interface design. However, every application environment is unique and properdue diligence is required to ensure a robust design. Careful attention must be given tofunctional testing through simulation, proper synthesis and implementation, adherence toPCB layout guidelines, and board verification through IBIS simulation and signal integrityanalysis.Send Feedback |
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