Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 228UG586 November 30, 2016 www.xilinx.comChapter 1: DDR3 and DDR2 SDRAM Memory Interface SolutionDebugging DDR3/DDR2 DesignsCalibration failures and data errors can occur for many reasons and the debug of theseerrors can be time consuming. This section is intended to provide a clear step-by-stepdebug process to quickly identify the root cause of the failure and move to resolution.To focus the debug of calibration or data errors, use the provided MIG Example Design onthe targeted board with the Debug Feature enabled through the MIG 7 series GUI. Thelatest MIG 7 series release should be used to generate the Example Design.Finding Help on Xilinx.comTo help in the design and debug process when using the MIG IP core, the Xilinx Supportweb page contains key resources such as product documentation, release notes, answerrecords, information about known issues, and links for obtaining further product support.DocumentationThis product guide is the main document associated with the MIG IP core. This guide, alongwith documentation related to all products that aid in the design process, can be found onthe Xilinx Support web page or by using the Xilinx Documentation Navigator.Download the Xilinx Documentation Navigator from the Downloads page. For moreinformation about this tool and the features available, open the online help afterinstallation.Solution CentersSee the Xilinx Solution Centers for support on devices, software tools, and intellectualproperty at all stages of the design cycle. Topics include design assistance, advisories, andtroubleshooting tips.The Solution Center specific to the MIG IP core core is located at the Xilinx MIG SolutionCenter.Answer RecordsAnswer Records include information about commonly encountered problems, helpfulinformation on how to resolve these problems, and any known issues with a Xilinx product.Answer Records are created and maintained daily ensuring that users have access to themost accurate information available.Send Feedback