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Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Contents
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 337UG586 November 30, 2016 www.xilinx.comChapter 2: QDR II+ Memory Interface SolutionCustomizing the CoreThe 7 series FPGAs QDR II+ SRAM interface solution is customizable to support severalconfigurations. The specific configuration is defined by Verilog parameters in the top-levelof the core. As per the OOC flow, none of the parameter values are passed down to the userdesign RTL file from the example design top RTL file. So, any design related parameterchange is not reflected in the user design logic. The MIG tool should be used to regeneratea design when parameters need to be changed. These parameters are summarized inTable 2-12.Table 2-12: 7 Series FPGAs QDR II+ SRAM Memory Interface Solution Configurable ParametersParameter Description OptionsMEM_TYPE This is the memory address bus width QDR2PLUSCLK_PERIOD This is the memory clock period (ps).BURST_LEN This is the memory data burst length. 4DATA_WIDTH This is the memory data bus width and can be set throughthe MIG tool. A maximum DATA_WIDTH of 36 is supported.BW_WIDTH This must be set to DATA_WIDTH /9NUM_DEVICES This is the number of memory devices used.MEM_RD_LATENCYThis specifies the number of memory clock cycles of readlatency of the memory device used. This is derived from thememory vendor data sheet.2.02.5FIXED_LATENCY_MODE This indicates whether or not to use a predefined latencyfor a read response from the memory to the client interface. 0, 1CPT_CLK_CQ_ONLY This indicates only one of the read clocks provided by thememory (rise clock) is used for the data capture. TRUEPHY_LATENCYThis indicates the desired latency through the PHY for aread from the time the read command is issued until theread data is returned on the client interface.CLK_STABLE This is the number of cycles to wait until the echo clocks arestable.(See memory vendordata sheet)IODELAY_GRP (1) This is a unique name for the IODELAY_CTRL that isprovided when multiple IP cores are used in the design.REFCLK_FREQ This is the reference clock frequency for IDELAYCTRLs. Thisparameter should not be changed. 200.0RST_ACT_LOWThis is the active-Low or active-High reset. This is set to 1when System Reset Polarity option is selected as active-Lowand set to 0 when the option is selected as active-High.0, 1IBUF_LPWR_MODE This enables or disables low power mode for the inputbuffers.ONOFFIODELAY_HP_MODEThis enables or disables high-performance mode within theIODELAY primitive. When set to OFF, the IODELAY operatesin low power mode at the expense of performance.ONOFFSend Feedback |
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