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Xilinx Zynq-7000 User Manual
Also see for 7 Series: User guideUser guideUser guideUser guide
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Contents
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Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 21UG586 November 30, 2016 www.xilinx.comChapter 1: DDR3 and DDR2 SDRAM Memory Interface SolutionUsing MIG in the Vivado Design SuiteThis section provides the steps to generate the Memory Interface Generator (MIG) IP coreusing the Vivado Design Suite and run implementation.1. Start the Vivado Design Suite (see Figure 1-1).2. To create a new project, click the Create New Project option shown in Figure 1-1 toopen the page as shown in Figure 1-2.X-Ref Target - Figure 1-1Figure 1-1: Vivado Design SuiteSend Feedback |
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