Xilinx Zynq-7000 User Manual

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Xilinx Zynq-7000 User Manual Manual pdf 163 page image

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 163UG586 November 30, 2016 www.xilinx.comChapter 1: DDR3 and DDR2 SDRAM Memory Interface SolutionInterfacing to the CoreThe Memory Controller can be connected using either the AXI4 slave interface, the UI, orthe native interface. The AXI4 slave interface provides an AXI4 memory-mapped compliantslave ideal for connecting to processor subsystems. The AXI4 slave interface converts itstransactions to pass them over the UI. The UI resembles a simple FIFO interface and alwaysreturns the data in order. The native interface offers higher performance in some situations,but is more challenging to use.The native interface contains no buffers and returns data as soon as possible, but the returndata might be out of order. The application must reorder the received data internally if thenative interface is used and reordering is enabled. The following sections describe timingprotocols of each interface and how they should be controlled.Note: For a multi-ported memory interface or an interface that is sending requests faster than theMIG can consume, putting a packet (store and forward) FIFO on the input side of the user logic sideof the crossbar is necessary. This allows it to buffer the requests and grants bursts to come out assoon as it is ready.AXI4 Slave InterfaceThe AXI4 slave interface follows the AXI4 memory-mapped slave protocol specification asdescribed in the ARM AMBA open specifications. See this specification [Ref 4] for thesignaling details of the AXI4 slave interface.AXI AddressingThe AXI address from the AXI master is a TRUE byte address. The AXI shim converts theaddress from the AXI master to the memory based on AXI SIZE and memory data width. TheLSBs of the AXI byte address are masked to 0, depending on the data width of the memoryarray. If the memory array is 64 bits (8 bytes) wide, AXI address[2:0] are ignored and treatedas 0. If the memory array is 16 bits (2 bytes) wide, AXI address[0] is ignored and treated as 0.DDR3 DRAM is accessed in blocks of eight DRAM words for a burst length of 8. The UI dataport is as wide as eight DRAM words for 4:1 PHY to Memory Controller (MC) clock ratiomode and four DRAM words for 2:1 PHY to MC clock ratio.Table 1-62: AXI Byte Address MaskingPHY to MC ClockRatio UI Data Width Memory InterfaceData Width AXI Byte Address [7:0] (LSBs)Masking4:164 8 A[7:0]128 16 A[7:1], 1’b0256 32 A[7:2], 2’b00512 64 A[7:3], 3’b000Send Feedback

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