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Xilinx ML605 Hardware User's Manual

Also see for ML605: User guideManualManualHardware Tutorial

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Contents
  1. revision history
  2. Table Of Contents
  3. Table Of Contents
  4. about this guide
  5. Additional Support Resources
  6. additional information
  7. Features
  8. block diagram
  9. Electrostatic Discharge Caution
  10. Virtex-6 XC6VLX240T-1FFG1156 FPGA
  11. I/O Voltage Rails
  12. Mb Platform Flash XL
  13. ML605 Flash Boot Options
  14. System ACE CF and CompactFlash Connector
  15. USB JTAG
  16. clock generation
  17. SMA Connectors (Differential)
  18. Multi-Gigabit Transceivers (GTX MGTs)
  19. PCI Express Endpoint Connectivity
  20. SFP Module Connector
  21. Tri-Speed Ethernet PHY
  22. SGMII GTX Transceiver Clock Generation
  23. USB-to-UART Bridge
  24. usb controller
  25. DVI Codec
  26. Kb NV Memory
  27. status leds
  28. Ethernet PHY Status LEDs
  29. FPGA INIT and DONE LEDs
  30. user leds
  31. User Pushbutton Switches
  32. User DIP Switch
  33. User SMA GPIO
  34. LCD Display (16 Character x 2 Lines)
  35. Switches
  36. FPGA_PROG_B Pushbutton SW4 (Active-Low)
  37. System ACE CF CompactFlash Image Select DIP Switch S1
  38. Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2
  39. VITA 57.1 FMC HPC Connector
  40. VITA 57.1 FMC LPC Connector
  41. power management
  42. Onboard Power Regulation
  43. system monitor
  44. configuration options
  45. Appendix A: Default Switch and Jumper Settings
  46. Appendix B: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout
  48. declaration of conformity
  49. Safety
Xilinx ML605 Hardware User's Manual Manual pdf 54 page image
54 www.xilinx.com ML605 Hardware User GuideUG534 (v1.9) February 26, 2019Chapter 1: ML605 Evaluation BoardUser SMA GPIOThe ML605 includes an pair of SMA connectors for GPIO as described in Figure 1-21 andTable 1-24.X-Ref Target - Figure 1-21Figure 1-21: User SMA GPIOUG534_21_072109USER SMA GPIO NJ56 32K10K-400E3J76 32K10K-400E3GND1SIG11 SIGGND2GND3GND4GND5GND6GND7GND1GND2GND3GND4GND5GND6GND7USER SMA GPIO P23456782345678Table 1-24: User SMA ConnectionsU1 FPGA Pin Schematic Net Name SMA PinW34 USER_SMA_GPIO_N J56.1V34 USER_SMA_GPIO_P J57.1Send Feedback
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