Xilinx ML605 Hardware User's Manual

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Xilinx ML605 Hardware User's Manual Manual pdf 40 page image

40 www.xilinx.com ML605 Hardware User GuideUG534 (v1.9) February 26, 2019Chapter 1: ML605 Evaluation BoardSGMII GTX Transceiver Clock GenerationAn Integrated Circuit Systems ICS844021I chip generates a high-quality, low-jitter, 125-MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clock is sent to theGTX driving the SGMII interface. Series AC coupling capacitors are also present to allowthe clock input of the FPGA to set the common mode voltage.Table 1-13 shows the connections and pin numbers for the PHY.CFG5 VCC 2.5V DIS_FC = 1 DIS_SLEEP = 1 HWCFG_MD[3] = 1CFG6 PHY_LED_RX SEL_BDT = 0 INT_POL = 1 75/50Ω= 0Table 1-12: Board Connections for PHY Configuration Pins (Cont’d)Pin Connection onBoardBit[2]Definition and ValueBit[1]Definition and ValueBit[0]Definition and ValueX-Ref Target - Figure 1-13Figure 1-13: Ethernet SGMII Clock - 125 MHzVDDA_SGMIICLKICS84402IIVDDA VDDVDD_SGMIICLKSGMIICLK_QO_C_P SGMIICLK_QO_PSGMIICLK_QO_NSGMIICLK_QO_C_NQ0NQ0OEGNDXTAL_OUTXTAL_IN1234U82125.00 MHz ClockGND_SGMIICLKSGMIICLK_XTAL_OUTSGMIICLK_XTAL_IN8765X325.000MHZR132DNP1%1/16WC55 10.1UF10V 2X5RC34733PF50VNPOC56 10.1UF10V 2X5R12C34833PF50VNPO1212UG534_13_111709Table 1-13: Ethernet PHYConnectionsU1 FPGA Pin Schematic Net Name U80 M88E1111Pin Number Pin NameAN14 PHY_MDIO 33 MDIOAP14 PHY_MDC 35 MDCAH14 PHY_INT 32 INT_BAH13 PHY_RESET 36 RESET_BAL13 PHY_CRS 115 CRSAK13 PHY_COL 114 COLAP11 PHY_RXCLK 7 RXCLKAG12 PHY_RXER 8 RXERAM13 PHY_RXCTL_RXDV 4 RXDVAN13 PHY_RXD0 3 RXD0AF14 PHY_RXD1 128 RXD1AE14 PHY_RXD2 126 RXD2AN12 PHY_RXD3 125 RXD3Send Feedback