Xilinx ML605 Hardware User's Manual

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Xilinx ML605 Hardware User's Manual Manual pdf 34 page image

34 www.xilinx.com ML605 Hardware User GuideUG534 (v1.9) February 26, 2019Chapter 1: ML605 Evaluation Board8. Multi-Gigabit Transceivers (GTX MGTs)The ML605 provides access to 20 MGTs.• Eight (8) of the MGTs are wired to the PCIe x8 Endpoint (P1) edge connector fingers• Eight (8) of the MGTs are wired to the FMC HPC connector (J64)• One (1) MGT is wired to SMA connectors (J26, J27)• One (1) MGTs is wired to the FMC LPC connector (J63)• One (1) MGT is wired to the SFP Module connector (P4)• One (1) MGT is used for an SGMII connection to the Ethernet PHY (U80)See the Virtex-6 FPGA GTX Transceivers User Guide (UG366) [Ref 12]X-Ref Target - Figure 1-10Figure 1-10: MGT ClockingICS854104100 MHz LVDS100 MHz in fromNo ConnectNo Connect No ConnectPCIe Fingers(HCSL)250 MHz LVDSGTX_X0Y19GTX_X0Y18GTX_X0Y17GTX_X0Y16GTX_X0Y15GTX_X0Y14GTX_X0Y13GTX_X0Y12GTX_X0Y11GTX_X0Y10GTX_X0Y09GTX_X0Y08GTX_X0Y07GTX_X0Y06GTX_X0Y05GTX_X0Y04GTX_X0Y03GTX_X0Y02GTX_X0Y01GTX_X0Y00PCIePCIeBANK_115BANK_114BANK_113BANK_112 BANK_116 SGMIISMASFPFMC#2PCIe Lane1PCIe Lane 2PCIe Lane 3PCIe Lane 4PCIe Lane 5PCIe Lane 6PCIe Lane 7PCIe Lane 8FMC#1FMC#1FMC#1FMC#1FMC#1FMC#1FMC#1FMC#1SMA xxx MHz LVDSFMC#2 LPC xxx MHz GBTCLK0 LVDSAC coupling on MezzSGMII 125 MHz LVDSFMC#1 HPC xxx MHz LVDS GBTCLK0REFCLK0REFCLK1REFCLK0REFCLK1REFCLK0REFCLK1REFCLK0REFCLK1REFCLK0REFCLK1AC coupling on MezzICS854104(LVDS)ICS854104(LVDS)FMC#1 HPC CLK3_M2CTo FPGA CLK3_M2C_IO CC pinFMC#1 HPC CLK2_M2CTo FPGA CLK2_M2C_IO CC pinAC coupling on MezzFMC#1 HPC xxx MHz LVDS GBTCLK1(LVDS)(LVDS)UG534_10_021012Note: xxx MHz = user specified frequencyICS874001Send Feedback