AXI Interface BasedML605/SP605 MicroBlazeProcessor SubsystemHardware TutorialUG669 (v3.0) March 15, 2011

Xilinx MicroBlaze ML605 Hardware Tutorial

revision history

Guide Contents

Additional Support Resources

Overview

Features

Block Diagram

Detailed Description

Virtex-6 XC6VLX240T-1FFG1156 FPGA

I/O Voltage Rails

MB DDR3 Memory SODIMM

Mb Platform Flash XL

ML605 Flash Boot Options

System ACE CF and CompactFlash Connector

USB JTAG

Clock Generation

SMA Connectors (Differential)

Multi-Gigabit Transceivers (GTX MGTs)

PCI Express Endpoint Connectivity

SFP Module Connector

Tri-Speed Ethernet PHY

SGMII GTX Transceiver Clock Generation

USB-to-UART Bridge

USB Controller

DVI Codec

Kb NV Memory

Status LEDs

Ethernet PHY Status LEDs

FPGA INIT and DONE LEDs

User LEDs

User Pushbutton Switches

User DIP Switch

User SMA GPIO

LCD Display (16 Character x 2 Lines)

Switches

FPGA_PROG_B Pushbutton SW4 (Active-Low)

System ACE CF CompactFlash Image Select DIP Switch S1

Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2

VITA 57.1 FMC HPC Connector

VITA 57.1 FMC LPC Connector

Power Management

Onboard Power Regulation

System Monitor

Configuration Options

connector pinout

ML605

about this guide

additional information

block diagram

Electrostatic Discharge Caution

clock generation

usb controller

status leds

user leds

power management

system monitor

configuration options

Appendix A: Default Switch and Jumper Settings

Appendix B: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout

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Safety

SP605

Xilinx MicroBlaze ML605 Hardware Tutorial

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