ii • Table of Contents4.9 FIFO Control Register................................................... 224.10 Acquisition Enable Register ......................................... 224.11 Clock Source Register.................................................. 234.12 High Level Programming.............................................. 244.13 Low Level Programming............................................... 24Chapter 5 Operation Theorem ............................255.1 A/D Conversion Procedure ........................................... 255.2 A/D Signal Source Control ............................................ 265.3 A/D Trigger Source Control .......................................... 275.3.1 Trigger Sources......................................................................... 275.3.2 Simultaneous Trigger for Multiple Cards ........................... 285.3.3 Trigger Modes............................................................................ 295.4 A/D Clock Source Control ............................................. 315.4.1 A/D Clock Sources.................................................................... 315.4.2 Internal Pacer Clock................................................................. 315.4.3 External Pacer Clock................................................................ 315.4.4 Multiple Cards Operation ........................................................ 325.5 A/D Data Transfer ......................................................... 335.5.1 AD Data Transfer....................................................................... 335.5.2 Simultaneous Sampling of 4 AD Channels ........................ 335.5.3 Total Data Throughput............................................................. 345.5.4 Maximum Acquiring Data Length ......................................... 345.5.5 Bus-mastering Data Transfer................................................. 345.5.6 Host Memory Operation .......................................................... 355.5.7 Summary..................................................................................... 365.6 AD Data Format ............................................................ 36Chapter 6 C/C++ Library.......................................385.1 Libraries Installation .................................................... 385.2 Programming Guide...................................................... 395.2.1 Naming Convention .................................................................. 395.2.2 Data Types.................................................................................. 396.3 _9812_Initial.................................................................. 406.4 _9812_Close ................................................................. 416.5 _9812_AD_DMA_Start ................................................... 416.6 _9812_AD_DMA_Status ................................................ 436.7 _9812_AD_DMA_Stop................................................... 446.8 _9812_Set_Clk_Src ....................................................... 446.9 _9812_Set_Clk_Rate ..................................................... 456.10 _9812_Set_Trig ............................................................. 466.11 W_9812_Alloc_DMA_Mem ............................................ 486.12 W_9812_Free_DMA_Mem ............................................. 50