ADLINK Technology NuDAQ PCI-9812/10 User Manual

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ADLINK Technology NuDAQ PCI-9812/10 User Manual Manual pdf 39 page image

Operation Theorem • 315.4 A/D Clock Source ControlThe AD clock source determines how the board regulates the timingof conversions when you are acquiring multiple samples from asingle channel or from a group of multiple channels. The A/D clocksources on the PCI-9812 must use pacer clock but not single shot,because the A/D converters are in a pipelined structure, whichneeds 8 conversion clock to complete the conversion of digital data.5.4.1 A/D Clock SourcesThe A/D converters operate under the paced mode, which usespacer clock for A/D conversion at a fixed rate. PCI-9812/10supports three clock sources for analog input conversion:l Internal A/D pacer clock (default);l External sine wave clock;l External square clock.The description of these three clock sources is in the following.5.4.2 Internal Pacer ClockAn on-board timer / counter is used as the internal A/D pacer clock.The frequency of the pacer is software controllable. The maximumpacer signal rate is 40Mz/2=20MHz, that is also the maximumsampling rate of PCI-9812/10. Note that 40MHz is the on-boardclock. The ADC sampling frequency is generated by feeding theclock source into a frequency divider. The following formuladetermines the ADC sampling frequency:Sampling Rate = Frequency of Source Clock / ADC ClockDivisorNote that the ADC Clock Divisor = 2,4,6,8,10… 1024 (maximum)5.4.3 External Pacer ClockUsers could connect an external pacer clock (sine or square wave)to the EXTCLK1 (pin 1) on JP1. Because users can handle theexternal signal with outside devices, the conversion rate of thismode is more flexible than the previous mode. When external clockis selected, this external clock is also divided by the frequencydivider as mentioned. Therefore the frequency of the external clockshould be at least twice as the desired sampling frequency. Theformula is shown as following: