ADLINK Technology NuDAQ PCI-9812/10 User Manual

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ADLINK Technology NuDAQ PCI-9812/10 User Manual Manual pdf 40 page image

32 • Operation TheoremSampling Rate = Frequency of Source Clock / ADC ClockDivisorNote: 1.The clock divider must be an even number, that is, the ADCClock Divisor = 2, 4, 6, 8, 10… 1024 (maximum), Theminimum divider value is 2.Please refer to section 6.2.6 andsection 6.2.7 to set the clock source and frequency divider.2.Because of the popelined architecture of the ADC, the first ADsample takes several clocks to convert, Therefore, theexternal clock must be continuous for correct AD poeration.5.4.4 Multiple Cards OperationWhen multiple cards are used in one system. The 4-channels onone card can achieve simultaneous conversion because of thesame internal clock source. However, the channels between twocards can not be synchronized because the clock sources ondifferent cards come from different sources. Even when the sameexternal clock source is applied to all cards, the A/D conversion timeis still possibly asynchronous because an on-board clock divider(divided by 2) is used. Therefore, when the same external clocksource is applied to multiple cards, the time difference of thesampling clocks between two cards will be half of the samplingclock period. The A/D clock can not synchronize the multiple cards.