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Sharp LH79525 manuals

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LH79525

Brand: Sharp | Category: Controller
Table of contents
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  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Overview
  34. Version
  35. Table 1-1. LH79524/LH79525 Differences
  36. Figure 1-1. LH79524/LH79525 Block Diagram
  37. Table 1-2. Clock Descriptions
  38. Figure 1-2. Standard Clocking Modes
  39. Figure 1-3. Fastbus Clocking Mode
  40. Table 1-3. Port C Settings For Boot
  41. Figure 1-4. Reset Circuit for TAP Controller
  42. Hardware Requirements at Reset
  43. Active Pull Ups
  44. AHB Bus Master Priority and Arbitration
  45. Table 1-5. AHB Memory Mapping
  46. Table 1-8. Internal SRAM Memory Section Mapping
  47. Table 1-11. Primary AHB Peripheral Register Mapping
  48. Table 1-12. APB Peripheral Register Mapping
  49. Instruction and Data Cache
  50. Theory of Operation
  51. Figure 2-1. ADC Block Diagram
  52. Bias-and-Control Network
  53. Figure 2-2. Bias-and-Control Network Block Diagram
  54. Clock Generator
  55. Figure 2-4. Example of a 4-bit SAR ADC Operation
  56. Battery Control Feature
  57. Timing Formulas
  58. Pen Interrupt
  59. Register Reference
  60. Register Descriptions
  61. Table 2-4. In + Mux Definition
  62. Low Word Register (LW)
  63. Results Register (RR)
  64. Interrupt Mask Register (IM)
  65. Power Configuration Register (PC)
  66. Table 2-13. Touch Screen Controller Power Modes
  67. General Configuration Register (GC)
  68. General Status Register (GS)
  69. Interrupt Status Register (IS)
  70. FIFO Status Register (FS)
  71. Control Bank Registers
  72. Idle High Word Register (IHWCTRL)
  73. Idle Low Word Register (ILWCTRL)
  74. Masked Interrupt Status Register (MIS)
  75. Interrupt Clear Register (IC)
  76. Figure 3-1. Boot Controller Block Diagram
  78. Table 3-1. Boot Configuration for Silicon Version A.0
  79. NAND Flash Operation
  80. NAND Flash Hardware Design
  81. Table 3-5. Supported Devices
  82. Booting from UART
  83. Register Definitions
  84. nCS1 Override Register (CS1OV)
  85. External Peripheral Mapping Register (EPM)
  86. Introduction
  87. LCD Panel Architecture
  88. CLCDC Features
  89. Figure 4-3. Color LCD Controller Block Diagram
  90. Supported Displays and Panels
  91. Pixel Serializer
  92. Table 4-3. Frame Buffer Pixel Storage Format [15:0]
  93. Palette RAM
  94. Grayscale Algorithm
  95. Table 4-6. Supported TFT, HR-TFT, and AD-TFT LCD Panels
  96. Table 4-9. Color STN Intensities From Gray-Scale Modulation
  97. LCD Data Multiplexing
  98. LCD Interface Timing Signals
  99. LCD Vertical Timing Signals
  100. LCD Power Sequencing at Turn-On and Turn-Off
  101. Minimizing a Retained Image on the LCD
  102. Advanced LCD Interface
  103. ALI Theory of Operation
  104. CLCDC Register Reference
  105. CLCDC Register Descriptions
  106. Vertical Timing Panel Control Register (TIMING1)
  107. Clock and Signal Polarity Control Register (TIMING2)
  108. Upper Panel Frame Buffer Base Address Register (UPBASE)
  109. Lower Panel Frame Buffer Base Address Register (LPBASE)
  110. Interrupt Enable Register (INTREN)
  111. CLCDC Control Register (CTRL)
  112. Table 4-27. CTRL Fields
  113. Raw Interrupt Status Register (STATUS)
  114. Masked Interrupt Status Register (INTERRUPT)
  115. Interrupt Clear Register (INTCLR)
  116. LCD Upper Panel and Lower Panel Frame Buffer Current Address Register (UPCURR and LPCURR)
  117. bit Color Palette Register (PALETTE)
  118. Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC)
  119. ALI Register Reference
  120. Control Register (ALICTRL)
  121. Timing Delay Register 1 (ALITIMING1)
  122. Timing Delay Register 2 (ALITIMING2)
  123. STN Horizontal Timing
  124. Figure 4-6. STN Horizontal Timing Diagram
  125. Figure 4-7. STN Vertical Timing Diagram
  126. Figure 4-8. TFT Horizontal Timing Diagram
  127. Figure 4-9. TFT Vertical Timing Diagram
  128. Figure 4-10. AD-TFT, HR-TFT Horizontal Timing Diagram
  129. Table 5-1. DMA Controller Stream Assignments and Request Priority
  130. Use for SSP and UART
  131. Interrupt, Error, and Status Registers
  132. Memory Map
  134. Destination Base Registers (DESTLO and DESTHI)
  135. Maximum Count Register (MAX)
  136. Control Register (CTRL)
  137. Table 5-16. DMA Data Width
  138. Table 5-18. Constraints on CTRL Field Values Based on Stream Type
  139. Current Source Registers (CURSHI and CURSLO)
  140. Current Destination Registers (CURDHI and CURDLO)
  141. Terminal Count Register (TCNT)
  142. Interrupt Mask Register (MASK)
  143. Interrupt Clear Register (CLR)
  144. Status Register (STATUS)
  146. Operational Overview
  147. Setup
  148. Table 6-1. Receive Buffer Descriptor LIst
  149. Transmit Buffer
  150. Receive Block
  151. Pause Frame Support
  152. Address Checking Block
  153. Broadcast Address
  154. Type ID Checking
  155. Initialization
  156. Figure 6-2. Address Matching
  157. Transmit Buffer List
  158. PHY Maintenance
  160. Control, Configuration, And Status Register Definitions
  161. Network Configuration Register (NETCONFIG)
  162. Network Status Register (NETSTATUS)
  163. Transmit Status Register (TXSTATUS)
  164. Receive Buffer Queue Pointer (RXBQP)
  165. Transmit Buffer Queue Pointer (TXBQP)
  166. Receive Status Register (RXSTATUS)
  167. Interrupt Status Register (INSTATUS)
  168. Interrupt Enable Register (ENABLE)
  169. Interrupt Disable Register (DISABLE)
  171. PHY Maintenance Register (PHYMAINT)
  172. Pause Time Register (PAUSETIME)
  173. Statistics Register Definitions
  174. Frames Transmitted OK (FRMTXOK)
  175. Multiple Collision Frames (MULTFRM)
  176. Frame Check Sequence Errors (FRCHK)
  177. Deferred Transmission Frames (DEFTXFRM)
  178. Excessive Collisions (EXCOL)
  179. Carrier Sense Errors (SENSERR)
  180. Receive Resource Errors (RXRERR)
  181. Receive Symbol Errors (RXSYMERR)
  182. Receive Jabbers (RXJAB)
  183. SQE Test Errors (SQERR)
  184. Transmitted Pause Frames (TXPAUSEFM)
  185. Matching Registers
  186. Specific Address 1 Bottom (SPECAD1BOT)
  187. Specific Address 2 Bottom (SPECAD2BOT)
  188. Specific Address 3 Bottom (SPECAD3BOT)
  189. Specific Address 4 Bottom (SPECAD4BOT)
  190. Type ID Checking (IDCHK)
  191. Figure 7-1. External Memory Controller Block Diagram
  192. External Memory Map
  193. Figure 7-2. Automatic Address Shifting
  194. Hardware Design
  195. Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices
  196. Figure 7-7. 32-bit Memory Bank Constructed From a Single 32-bit Device
  197. Figure 7-8. Typical Memory Connection Diagram
  198. Software Design
  199. Static Memory Device Selection
  200. Figure 7-10. Static Read Transaction with Zero Wait States
  201. Figure 7-11. Static Read Transaction with Three Wait States
  202. Figure 7-12. Static Write Transaction with Zero Wait States
  203. Figure 7-13. Static Write Transaction with Two Wait States
  204. Bus Turnaround
  205. Extended Wait Transfers
  206. Table 7-2. Boot Configuration for Silicon Version A.0
  207. Figure 7-14. Connection to NAND Flash
  208. General NAND Flash Access
  209. bit Example Transaction
  210. Dynamic Memory
  211. Table 7-6. 32-bit Wide Data Bus Address Mapping, SDRAM (BRC)
  212. Table 7-7. 16-bit Wide Data Bus Address Mapping, SDRAM (RBC)
  213. Table 7-8. 16-bit Wide Data Bus Address Mapping, SDRAM (BRC)
  214. Data Mask Signals
  218. Configuration Register (CONFIG)
  219. Dynamic Memory Control Register (DYNMCTRL)
  220. Dynamic Refresh Register (DYNMREF)
  221. Dynamic Memory Read Configuration Register (DYNMRCON)
  222. Dynamic Precharge Command Period Register (PRECHARGE)
  223. Dynamic Memory Active to Precharge Command Period Register (DYNM2PRE)
  224. Dynamic Memory Self-Refresh Exit Time Register (REFEXIT)
  225. Dynamic Memory Last Data Out to Active Time Register (DOACTIVE)
  226. Dynamic Memory Data-In to Active Time Register (DIACTIVE)
  227. Dynamic Memory Write Recovery Time Register (DWRT)
  228. Dynamic Memory Active to Active Command Period Register (DYNACTCMD)
  229. Dynamic Memory Auto-Refresh Period, and Auto-Refresh to Active Command Period Register (DYNAUTO)
  230. Dynamic Memory Exit Self-Refresh to Active Command Time Register (DYNREFEXIT)
  231. Dynamic Memory Active Bank A to Active Bank B Time Register (DYNACTIVEAB)
  232. Dynamic Memory Load Mode Register to Active Command Time Register (DYNAMICTMRD)
  233. Static Memory Extended Wait Register (WAIT)
  234. Dynamic Configuration Register for nDCS0 and nDCS1 (DYNCFGx)
  235. Table 7-49. Address Mapping
  236. Dynamic Memory RAS and CAS Delay Register for nDCS0 and nDCS1 (DYNRASCASx)
  237. Static Memory Configuration Register (SCONFIGx)
  238. Static Memory Write Enable Delay Registers (SWAITWENx)
  239. Static Memory Output Enable Delay Registers (SWAITOENx)
  240. Static Memory Read Delay Registers (SWAITRDx)
  241. Table 7-60. SWAITPAGEx Register
  242. Static Memory Write Delay Registers (SWAITWRx)
  243. Static Memory Turn Around Delay Registers (STURNx)
  245. Multiplexing
  246. Table 8-3. LH79525 GPIO Multiplexing
  249. Port B/D/F/H/J/L/N Data Register (P2DRx)
  250. Port A/C/E/G/I/K Data Direction Register (P1DDRx)
  251. Port B/D/F/H/L/N Data Direction Register
  253. Interrupt Handling
  254. Slave Mode
  257. Table 9-6. ICSAR Register
  258. Table 9-8. ICUSAR Register
  259. Table 9-12. ICHCNT Register
  260. Table 9-16. ICSTAT Register
  262. Driving/Latching Edges
  263. Transmission
  264. Slave Mode Transmission
  265. Reception
  266. Slave Mode Reception
  267. Suppression of SSPFSSIN
  268. Interrupts
  269. Receive Interrupt
  272. Table 10-4. WSINV Functionality
  273. Status Register (STAT)
  274. Interrupt Mask Set or Clear Register (IMSC)
  275. Raw Interrupt Status Register (RIS)
  277. Interrupt Clear Register (ICR)
  280. Resistor Configuration Control 1 Register (RESCTL1)
  281. Multiplexing Control 3 Register (MUXCTL3)
  282. Multiplexing Control 4 Register (MUXCTL4)
  283. Resistor Configuration Control 4 Register (RESCTL4)
  284. Multiplexing Control 5 Register (MUXCTL5)
  285. Resistor Configuration Control 5 Register (RESCTL5)
  286. Multiplexing Control 6 Register (MUXCTL6)
  287. Resistor Configuration Control 6 Register (RESCTL6)
  288. Multiplexing Control 7 Register (MUXCTL7)
  289. Resistor Configuration Control 7 Register (RESCTL7)
  290. Multiplexing Control 10 Register (MUXCTL10)
  291. Resistor Configuration Control 10 Register (RESCTL10)
  292. Multiplexing Control 11 Register (MUXCTL11)
  293. Resistor Configuration Control 11 Register (RESCTL11)
  294. Multiplexing Control 12 Register (MUXCTL12)
  295. Resistor Configuration Control 12 Register (RESCTL12)
  296. Resistor Configuration Control 13 Register (RESCTL13)
  297. Multiplexing Control 14 Register (MUXCTL14)
  298. Multiplexing Control 15 Register (MUXCTL15)
  299. Resistor Configuration Control 17 Register (RESCTL17)
  300. Multiplexing Control 19 Register (MUXCTL19)
  301. Resistor Configuration Control 19 Register (RESCTL19)
  302. Multiplexing Control 20 Register (MUXCTL20)
  303. Resistor Configuration Control 20 Register (RESCTL20)
  304. Multiplexing Control 21 Register (MUXCTL21)
  305. Resistor Configuration Control 21 Register (RESCTL21)
  306. Multiplexing Control 22 Register (MUXCTL22)
  307. Resistor Configuration Control 22 Register (RESCTL22)
  308. Multiplexing Control 23 Register (MUXCTL23)
  309. Resistor Configuration Control 23 Register (RESCTL23)
  310. Multiplexing Control 24 Register (MUXCTL24)
  311. Resistor Configuration Control 24 Register (RESCTL24)
  312. Multiplexing Control 25 Register (MUXCTL25)
  314. Configuring the RTC for Use
  316. Match Register (MR)
  317. Control Register (CR)
  321. System PLL and USB PLL Reset
  322. Peripheral Block Clocks
  323. Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies
  324. Power Modes
  325. Stop2 Mode
  328. Identification Register (CHIPID)
  329. Remap Control Register (REMAP)
  330. Figure 13-4. Remap = 0b01
  331. Figure 13-6. Remap = 0b11
  332. Software Reset Register (SOFTRESET)
  333. Reset Status Register (RSTSTATUS)
  334. Reset Status Clear Register (RSTSTATUSCLR)
  335. System Clock Prescaler Register (SYSCLKPRE)
  336. CPU Clock Prescaler Register (CPUCLKPRE)
  337. Peripheral Clock Control Register 0 (PCLKCTRL0)
  338. Peripheral Clock Control Register 1 (PCLKCTRL1)
  339. AHB Clock Control Register (AHBCLKCTRL)
  340. Peripheral Clock Select Register 0 (PCLKSEL0)
  341. Peripheral Clock Select Register 1 (PCLKSEL1)
  342. Silicon Revision Register (SILICONREV)
  343. LCD Clock Prescaler Register (LCDPRE)
  344. SSP Clock Prescaler Register (SSPPRE)
  345. ADC Clock Prescaler Register (ADCPRE)
  346. USB Clock Prescaler Register (USBPRE)
  347. External Interrupt Configuration Register (INTCONFIG)
  348. External Interrupt Clear Register (INTCLR)
  349. Core Clock Configuration Register (CORECONFIG)
  350. System PLL Control Register (SYSPLLCTL)
  351. USB PLL Control Register (USBPLLCTL)
  353. Table 14-1. Feature Comparison
  354. Timing Waveforms
  355. Motorola SPI Frame Format
  356. Texas Instruments Frame Format
  357. National Semiconductor Frame Format
  358. Clock Generation
  359. Transmit Interrupt
  362. Control Register 1 (CTRL1)
  363. Data Register – Receive/Transmit FIFO Register (DR)
  364. Status Register (SR)
  365. Clock Prescale Register (CPSR)
  366. Interrupt Mask Set and Clear Register (IMSC)
  370. DMA Control Register (DCR)
  372. Counter Clear Upon Compare Match
  373. Capture Signal Sampling
  374. Timer Interrupts
  377. Timer 0 Compare/Capture Control Register (CMP_CAP_CTRL0)
  378. Timer 0 Interrupt Control Register (INTEN0)
  379. Timer 0 Status Register (STATUS0)
  380. Timer 0 Counter Register (CNT0)
  381. Timer 0 Compare Registers (T0CMPn)
  382. Timer 0 Capture Registers (CAPn)
  383. Timer 1 Control Register (CTRL1)
  384. Timer 1 Interrupt Control Register (INTEN1)
  385. Timer 1 Status Register (STATUS1)
  386. Timer 1 Counter Register (CNT1)
  387. Timer 1 Compare Registers (T1CMPn)
  388. Timer 1 Capture Registers (T1CAPn)
  389. Timer 2 Control Register (CTRL2)
  390. Timer 2 Interrupt Control Register (INTEN2)
  391. Timer 2 Status Register (STATUS2)
  392. Timer 2 Counter Register (CNT2)
  393. Timer 2 Compare Registers (T2CMPn)
  394. Timer 2 Capture Registers (T2CAPn)
  396. Transmitting Data
  397. Nine-bit Mode
  398. On-Chip DMA Capabilities
  399. Hardware Flow Control
  402. Receive Status/Error Clear Register (UARTRSR/UARTECR)
  403. Table 16-8. UARTRSR/UARTECR Register (Read Operations)
  404. Flag Register (UARTFR)
  405. IrDA Low-Power Counter Register (UARTILPR)
  406. Integer Baud Rate Divisor Register (UARTIBRD)
  407. Fractional Baud Rate Divisor Register (UARTFBRD)
  408. Line Control Register (UARTLCR_H)
  409. Table 16-21. Truth Table for 9BIT, SPS, EPS, and PEN bits
  410. UART Control Register (UARTCR)
  411. Interrupt FIFO Level Select Register (UARTIFLS)
  412. Interrupt Mask Set/Clear Register (UARTIMSC)
  413. Raw Interrupt Status Register (UARTRIS)
  414. Masked Interrupt Status Register (UARTMIS)
  415. Interrupt Clear Register (UARTICR)
  416. UART0 DMA Control Register (DMACTRL)
  418. Endpoints
  419. Isochronous Endpoints
  420. DMA Interface
  421. DMA Operation
  422. DMA Mode 1: OUT Endpoints
  423. DMA Mode 1: IN Endpoints
  426. Power Management Register (PMR)
  427. Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR)
  428. Interrupt Register for OUT Endpoint 1 and 2 (OIR)
  429. Interrupt Register for common USB interrupts (UIR)
  430. IN Interrupt Enable Register (IIE)
  431. OUT Interrupt Enable Register (OIE)
  432. Interrupt Enable Register (UIE)
  433. Frame Number Registers (FRAMEx)
  434. Indexed Registers
  435. IN Maximum Packet Size Register (INMAXP)
  436. Control Status Register for EP 0 (CSR0)
  437. Control Status Register 1 for IN EP 1, 2, and 3 (INCSR1)
  438. Control Status Register 2 for IN EP 1, 2, and 3 (INCSR2)
  439. OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP)
  440. Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR1)
  441. Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2)
  442. Count 0 Register (OUTCOUNT0)
  443. Out Count 2 Register (OUTCOUNT2)
  444. Pending DMA Interrupts Register (INTR)
  445. DMA Channel x Control Register (CNTLx)
  446. DMA Channel x AHB Memory Address Register
  448. VIC Interrupt Listing
  449. Vectored Interrupts
  450. Clearing Interrupts
  453. FIQ Status Register (FIQSTATUS)
  454. Interrupt Select Register (INTSELECT)
  455. Interrupt Enable Clear Register (INTENCLEAR)
  456. Software Interrupt Register (SOFTINT)
  457. Software Interrupt Clear Register (SOFTINTCLEAR)
  458. Vector Address Register (VECTADDR)
  459. Vector Address Registers (VECTADDRx)
  460. Vector Control Registers (VECTCTRLx)
  461. Interrupt Test Output Register (ITOP)
  463. Figure 19-1. Watchdog Timer Block Diagram
  464. WDT Operation Details
  467. Counter Reset Register (RST)
  469. Current Watchdog Count Registers (COUNT[3:0])
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