LH79524/LH79525 User’s Guide I2 S ConverterVersion 1.0 10-1510.2.2.1.1 Implementation of WSDELWSDEL is used to delay the assertion of the frame input/output. During master mode, ifWSDEL = 1, then the frame output from the SSP is delayed by one clock before beingasserted on the PB2/SSPFRM/I2SWS pin. If WSDEL = 0, then frame output is passedthrough without additional delay. During slave mode, if WDSEL = 0 the frame input isdelayed by one clock before being asserted to the SSP so that the SSPFSSIN pulse coin-cides with the MSB of the data. If WSDEL = 1, the frame input is passed to the SSP withoutadditional delay.10.2.2.1.2 Implementation of WSINVAs seen in Table 10-4, if the WSINV = 0, a logic low on the PB2/SSPFRM/I2SWS pin indi-cates that the left channel is transmitting, while a logic high indicates that the right channelis transmitting. If the WSINV bit is set, then a logic low on the PB2/SSPFRM/I2SWS pinindicates that the right channel is transmitting, while a logic high indicates that the leftchannel is transmitting. After reset, the default value of WSINV is a logic low, indicating theleft channel.Table 10-4. WSINV FunctionalityWSINV PB2/SSPFRM/I2SWS = 0 PB2/SSPFRM/I2SWS = 10 Left Right1 Right Left
