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Sharp LH79524 User Manual Manual pdf 275 page image

Sharp LH79524 User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. Table Of Contents
  21. Table Of Contents
  22. Table Of Contents
  23. Table Of Contents
  24. Table Of Contents
  25. Table Of Contents
  26. Table Of Contents
  27. Table Of Contents
  28. Table Of Contents
  29. Table Of Contents
  30. Table Of Contents
  31. Table Of Contents
  32. Table Of Contents
  33. Overview
  34. Version
  35. Table 1-1. LH79524/LH79525 Differences
  36. Figure 1-1. LH79524/LH79525 Block Diagram
  37. Table 1-2. Clock Descriptions
  38. Figure 1-2. Standard Clocking Modes
  39. Figure 1-3. Fastbus Clocking Mode
  40. Table 1-3. Port C Settings For Boot
  41. Figure 1-4. Reset Circuit for TAP Controller
  42. Hardware Requirements at Reset
  43. Active Pull Ups
  44. AHB Bus Master Priority and Arbitration
  45. Table 1-5. AHB Memory Mapping
  46. Table 1-8. Internal SRAM Memory Section Mapping
  47. Table 1-11. Primary AHB Peripheral Register Mapping
  48. Table 1-12. APB Peripheral Register Mapping
  49. Instruction and Data Cache
  50. Theory of Operation
  51. Figure 2-1. ADC Block Diagram
  52. Bias-and-Control Network
  53. Figure 2-2. Bias-and-Control Network Block Diagram
  54. Clock Generator
  55. Figure 2-4. Example of a 4-bit SAR ADC Operation
  56. Battery Control Feature
  57. Timing Formulas
  58. Pen Interrupt
  59. Register Reference
  60. Register Descriptions
  61. Table 2-4. In + Mux Definition
  62. Low Word Register (LW)
  63. Results Register (RR)
  64. Interrupt Mask Register (IM)
  65. Power Configuration Register (PC)
  66. Table 2-13. Touch Screen Controller Power Modes
  67. General Configuration Register (GC)
  68. General Status Register (GS)
  69. Interrupt Status Register (IS)
  70. FIFO Status Register (FS)
  71. Control Bank Registers
  72. Idle High Word Register (IHWCTRL)
  73. Idle Low Word Register (ILWCTRL)
  74. Masked Interrupt Status Register (MIS)
  75. Interrupt Clear Register (IC)
  76. Figure 3-1. Boot Controller Block Diagram
  77. Table 3-1. Boot Configuration for Silicon Version A.0
  78. NAND Flash Operation
  79. NAND Flash Hardware Design
  80. Table 3-5. Supported Devices
  81. Booting from UART
  82. Register Definitions
  83. nCS1 Override Register (CS1OV)
  84. External Peripheral Mapping Register (EPM)
  85. Introduction
  86. LCD Panel Architecture
  87. CLCDC Features
  88. Figure 4-3. Color LCD Controller Block Diagram
  89. Supported Displays and Panels
  90. Pixel Serializer
  91. Table 4-3. Frame Buffer Pixel Storage Format [15:0]
  92. Palette RAM
  93. Grayscale Algorithm
  94. Table 4-6. Supported TFT, HR-TFT, and AD-TFT LCD Panels
  95. Table 4-9. Color STN Intensities From Gray-Scale Modulation
  96. LCD Data Multiplexing
  97. LCD Interface Timing Signals
  98. LCD Vertical Timing Signals
  99. LCD Power Sequencing at Turn-On and Turn-Off
  100. Minimizing a Retained Image on the LCD
  101. Advanced LCD Interface
  102. ALI Theory of Operation
  103. CLCDC Register Reference
  104. CLCDC Register Descriptions
  105. Vertical Timing Panel Control Register (TIMING1)
  106. Clock and Signal Polarity Control Register (TIMING2)
  107. Upper Panel Frame Buffer Base Address Register (UPBASE)
  108. Lower Panel Frame Buffer Base Address Register (LPBASE)
  109. Interrupt Enable Register (INTREN)
  110. CLCDC Control Register (CTRL)
  111. Table 4-27. CTRL Fields
  112. Raw Interrupt Status Register (STATUS)
  113. Masked Interrupt Status Register (INTERRUPT)
  114. Interrupt Clear Register (INTCLR)
  115. LCD Upper Panel and Lower Panel Frame Buffer Current Address Register (UPCURR and LPCURR)
  116. bit Color Palette Register (PALETTE)
  117. Table 4-40. PALETTE Register (LH79524 with 16-Bit CLCDC)
  118. ALI Register Reference
  119. Control Register (ALICTRL)
  120. Timing Delay Register 1 (ALITIMING1)
  121. Timing Delay Register 2 (ALITIMING2)
  122. STN Horizontal Timing
  123. Figure 4-6. STN Horizontal Timing Diagram
  124. Figure 4-7. STN Vertical Timing Diagram
  125. Figure 4-8. TFT Horizontal Timing Diagram
  126. Figure 4-9. TFT Vertical Timing Diagram
  127. Figure 4-10. AD-TFT, HR-TFT Horizontal Timing Diagram
  128. Table 5-1. DMA Controller Stream Assignments and Request Priority
  129. Use for SSP and UART
  130. Interrupt, Error, and Status Registers
  131. Memory Map
  132. Destination Base Registers (DESTLO and DESTHI)
  133. Maximum Count Register (MAX)
  134. Control Register (CTRL)
  135. Table 5-16. DMA Data Width
  136. Table 5-18. Constraints on CTRL Field Values Based on Stream Type
  137. Current Source Registers (CURSHI and CURSLO)
  138. Current Destination Registers (CURDHI and CURDLO)
  139. Terminal Count Register (TCNT)
  140. Interrupt Mask Register (MASK)
  141. Interrupt Clear Register (CLR)
  142. Status Register (STATUS)
  143. Operational Overview
  144. Setup
  145. Table 6-1. Receive Buffer Descriptor LIst
  146. Transmit Buffer
  147. Receive Block
  148. Pause Frame Support
  149. Address Checking Block
  150. Broadcast Address
  151. Type ID Checking
  152. Initialization
  153. Figure 6-2. Address Matching
  154. Transmit Buffer List
  155. PHY Maintenance
  156. Control, Configuration, And Status Register Definitions
  157. Network Configuration Register (NETCONFIG)
  158. Network Status Register (NETSTATUS)
  159. Transmit Status Register (TXSTATUS)
  160. Receive Buffer Queue Pointer (RXBQP)
  161. Transmit Buffer Queue Pointer (TXBQP)
  162. Receive Status Register (RXSTATUS)
  163. Interrupt Status Register (INSTATUS)
  164. Interrupt Enable Register (ENABLE)
  165. Interrupt Disable Register (DISABLE)
  166. PHY Maintenance Register (PHYMAINT)
  167. Pause Time Register (PAUSETIME)
  168. Statistics Register Definitions
  169. Frames Transmitted OK (FRMTXOK)
  170. Multiple Collision Frames (MULTFRM)
  171. Frame Check Sequence Errors (FRCHK)
  172. Deferred Transmission Frames (DEFTXFRM)
  173. Excessive Collisions (EXCOL)
  174. Carrier Sense Errors (SENSERR)
  175. Receive Resource Errors (RXRERR)
  176. Receive Symbol Errors (RXSYMERR)
  177. Receive Jabbers (RXJAB)
  178. SQE Test Errors (SQERR)
  179. Transmitted Pause Frames (TXPAUSEFM)
  180. Matching Registers
  181. Specific Address 1 Bottom (SPECAD1BOT)
  182. Specific Address 2 Bottom (SPECAD2BOT)
  183. Specific Address 3 Bottom (SPECAD3BOT)
  184. Specific Address 4 Bottom (SPECAD4BOT)
  185. Type ID Checking (IDCHK)
  186. Figure 7-1. External Memory Controller Block Diagram
  187. External Memory Map
  188. Figure 7-2. Automatic Address Shifting
  189. Hardware Design
  190. Figure 7-3. 32-bit Memory Bank Constructed From 8-bit Devices
  191. Figure 7-7. 32-bit Memory Bank Constructed From a Single 32-bit Device
  192. Figure 7-8. Typical Memory Connection Diagram
  193. Software Design
  194. Static Memory Device Selection
  195. Figure 7-10. Static Read Transaction with Zero Wait States
  196. Figure 7-11. Static Read Transaction with Three Wait States
  197. Figure 7-12. Static Write Transaction with Zero Wait States
  198. Figure 7-13. Static Write Transaction with Two Wait States
  199. Bus Turnaround
  200. Extended Wait Transfers
  201. Table 7-2. Boot Configuration for Silicon Version A.0
  202. Figure 7-14. Connection to NAND Flash
  203. General NAND Flash Access
  204. bit Example Transaction
  205. Dynamic Memory
  206. Table 7-6. 32-bit Wide Data Bus Address Mapping, SDRAM (BRC)
  207. Table 7-7. 16-bit Wide Data Bus Address Mapping, SDRAM (RBC)
  208. Table 7-8. 16-bit Wide Data Bus Address Mapping, SDRAM (BRC)
  209. Data Mask Signals
  210. Configuration Register (CONFIG)
  211. Dynamic Memory Control Register (DYNMCTRL)
  212. Dynamic Refresh Register (DYNMREF)
  213. Dynamic Memory Read Configuration Register (DYNMRCON)
  214. Dynamic Precharge Command Period Register (PRECHARGE)
  215. Dynamic Memory Active to Precharge Command Period Register (DYNM2PRE)
  216. Dynamic Memory Self-Refresh Exit Time Register (REFEXIT)
  217. Dynamic Memory Last Data Out to Active Time Register (DOACTIVE)
  218. Dynamic Memory Data-In to Active Time Register (DIACTIVE)
  219. Dynamic Memory Write Recovery Time Register (DWRT)
  220. Dynamic Memory Active to Active Command Period Register (DYNACTCMD)
  221. Dynamic Memory Auto-Refresh Period, and Auto-Refresh to Active Command Period Register (DYNAUTO)
  222. Dynamic Memory Exit Self-Refresh to Active Command Time Register (DYNREFEXIT)
  223. Dynamic Memory Active Bank A to Active Bank B Time Register (DYNACTIVEAB)
  224. Dynamic Memory Load Mode Register to Active Command Time Register (DYNAMICTMRD)
  225. Static Memory Extended Wait Register (WAIT)
  226. Dynamic Configuration Register for nDCS0 and nDCS1 (DYNCFGx)
  227. Table 7-49. Address Mapping
  228. Dynamic Memory RAS and CAS Delay Register for nDCS0 and nDCS1 (DYNRASCASx)
  229. Static Memory Configuration Register (SCONFIGx)
  230. Static Memory Write Enable Delay Registers (SWAITWENx)
  231. Static Memory Output Enable Delay Registers (SWAITOENx)
  232. Static Memory Read Delay Registers (SWAITRDx)
  233. Table 7-60. SWAITPAGEx Register
  234. Static Memory Write Delay Registers (SWAITWRx)
  235. Static Memory Turn Around Delay Registers (STURNx)
  236. Multiplexing
  237. Table 8-3. LH79525 GPIO Multiplexing
  238. Port B/D/F/H/J/L/N Data Register (P2DRx)
  239. Port A/C/E/G/I/K Data Direction Register (P1DDRx)
  240. Port B/D/F/H/L/N Data Direction Register
  241. Interrupt Handling
  242. Slave Mode
  243. Table 9-6. ICSAR Register
  244. Table 9-8. ICUSAR Register
  245. Table 9-12. ICHCNT Register
  246. Table 9-16. ICSTAT Register
  247. Driving/Latching Edges
  248. Transmission
  249. Slave Mode Transmission
  250. Reception
  251. Slave Mode Reception
  252. Suppression of SSPFSSIN
  253. Interrupts
  254. Receive Interrupt
  255. Table 10-4. WSINV Functionality
  256. Status Register (STAT)
  257. Interrupt Mask Set or Clear Register (IMSC)
  258. Raw Interrupt Status Register (RIS)
  259. Interrupt Clear Register (ICR)
  260. Resistor Configuration Control 1 Register (RESCTL1)
  261. Multiplexing Control 3 Register (MUXCTL3)
  262. Multiplexing Control 4 Register (MUXCTL4)
  263. Resistor Configuration Control 4 Register (RESCTL4)
  264. Multiplexing Control 5 Register (MUXCTL5)
  265. Resistor Configuration Control 5 Register (RESCTL5)
  266. Multiplexing Control 6 Register (MUXCTL6)
  267. Resistor Configuration Control 6 Register (RESCTL6)
  268. Multiplexing Control 7 Register (MUXCTL7)
  269. Resistor Configuration Control 7 Register (RESCTL7)
  270. Multiplexing Control 10 Register (MUXCTL10)
  271. Resistor Configuration Control 10 Register (RESCTL10)
  272. Multiplexing Control 11 Register (MUXCTL11)
  273. Resistor Configuration Control 11 Register (RESCTL11)
  274. Multiplexing Control 12 Register (MUXCTL12)
  275. Resistor Configuration Control 12 Register (RESCTL12)
  276. Resistor Configuration Control 13 Register (RESCTL13)
  277. Multiplexing Control 14 Register (MUXCTL14)
  278. Multiplexing Control 15 Register (MUXCTL15)
  279. Resistor Configuration Control 17 Register (RESCTL17)
  280. Multiplexing Control 19 Register (MUXCTL19)
  281. Resistor Configuration Control 19 Register (RESCTL19)
  282. Multiplexing Control 20 Register (MUXCTL20)
  283. Resistor Configuration Control 20 Register (RESCTL20)
  284. Multiplexing Control 21 Register (MUXCTL21)
  285. Resistor Configuration Control 21 Register (RESCTL21)
  286. Multiplexing Control 22 Register (MUXCTL22)
  287. Resistor Configuration Control 22 Register (RESCTL22)
  288. Multiplexing Control 23 Register (MUXCTL23)
  289. Resistor Configuration Control 23 Register (RESCTL23)
  290. Multiplexing Control 24 Register (MUXCTL24)
  291. Resistor Configuration Control 24 Register (RESCTL24)
  292. Multiplexing Control 25 Register (MUXCTL25)
  293. Configuring the RTC for Use
  294. Match Register (MR)
  295. Control Register (CR)
  296. System PLL and USB PLL Reset
  297. Peripheral Block Clocks
  298. Table 13-1. LH79524/LH79525 Clocks and Maximum Frequencies
  299. Power Modes
  300. Stop2 Mode
  301. Identification Register (CHIPID)
  302. Remap Control Register (REMAP)
  303. Figure 13-4. Remap = 0b01
  304. Figure 13-6. Remap = 0b11
  305. Software Reset Register (SOFTRESET)
  306. Reset Status Register (RSTSTATUS)
  307. Reset Status Clear Register (RSTSTATUSCLR)
  308. System Clock Prescaler Register (SYSCLKPRE)
  309. CPU Clock Prescaler Register (CPUCLKPRE)
  310. Peripheral Clock Control Register 0 (PCLKCTRL0)
  311. Peripheral Clock Control Register 1 (PCLKCTRL1)
  312. AHB Clock Control Register (AHBCLKCTRL)
  313. Peripheral Clock Select Register 0 (PCLKSEL0)
  314. Peripheral Clock Select Register 1 (PCLKSEL1)
  315. Silicon Revision Register (SILICONREV)
  316. LCD Clock Prescaler Register (LCDPRE)
  317. SSP Clock Prescaler Register (SSPPRE)
  318. ADC Clock Prescaler Register (ADCPRE)
  319. USB Clock Prescaler Register (USBPRE)
  320. External Interrupt Configuration Register (INTCONFIG)
  321. External Interrupt Clear Register (INTCLR)
  322. Core Clock Configuration Register (CORECONFIG)
  323. System PLL Control Register (SYSPLLCTL)
  324. USB PLL Control Register (USBPLLCTL)
  325. Table 14-1. Feature Comparison
  326. Timing Waveforms
  327. Motorola SPI Frame Format
  328. Texas Instruments Frame Format
  329. National Semiconductor Frame Format
  330. Clock Generation
  331. Transmit Interrupt
  332. Control Register 1 (CTRL1)
  333. Data Register – Receive/Transmit FIFO Register (DR)
  334. Status Register (SR)
  335. Clock Prescale Register (CPSR)
  336. Interrupt Mask Set and Clear Register (IMSC)
  337. DMA Control Register (DCR)
  338. Counter Clear Upon Compare Match
  339. Capture Signal Sampling
  340. Timer Interrupts
  341. Timer 0 Compare/Capture Control Register (CMP_CAP_CTRL0)
  342. Timer 0 Interrupt Control Register (INTEN0)
  343. Timer 0 Status Register (STATUS0)
  344. Timer 0 Counter Register (CNT0)
  345. Timer 0 Compare Registers (T0CMPn)
  346. Timer 0 Capture Registers (CAPn)
  347. Timer 1 Control Register (CTRL1)
  348. Timer 1 Interrupt Control Register (INTEN1)
  349. Timer 1 Status Register (STATUS1)
  350. Timer 1 Counter Register (CNT1)
  351. Timer 1 Compare Registers (T1CMPn)
  352. Timer 1 Capture Registers (T1CAPn)
  353. Timer 2 Control Register (CTRL2)
  354. Timer 2 Interrupt Control Register (INTEN2)
  355. Timer 2 Status Register (STATUS2)
  356. Timer 2 Counter Register (CNT2)
  357. Timer 2 Compare Registers (T2CMPn)
  358. Timer 2 Capture Registers (T2CAPn)
  359. Transmitting Data
  360. Nine-bit Mode
  361. On-Chip DMA Capabilities
  362. Hardware Flow Control
  363. Receive Status/Error Clear Register (UARTRSR/UARTECR)
  364. Table 16-8. UARTRSR/UARTECR Register (Read Operations)
  365. Flag Register (UARTFR)
  366. IrDA Low-Power Counter Register (UARTILPR)
  367. Integer Baud Rate Divisor Register (UARTIBRD)
  368. Fractional Baud Rate Divisor Register (UARTFBRD)
  369. Line Control Register (UARTLCR_H)
  370. Table 16-21. Truth Table for 9BIT, SPS, EPS, and PEN bits
  371. UART Control Register (UARTCR)
  372. Interrupt FIFO Level Select Register (UARTIFLS)
  373. Interrupt Mask Set/Clear Register (UARTIMSC)
  374. Raw Interrupt Status Register (UARTRIS)
  375. Masked Interrupt Status Register (UARTMIS)
  376. Interrupt Clear Register (UARTICR)
  377. UART0 DMA Control Register (DMACTRL)
  378. Endpoints
  379. Isochronous Endpoints
  380. DMA Interface
  381. DMA Operation
  382. DMA Mode 1: OUT Endpoints
  383. DMA Mode 1: IN Endpoints
  384. Power Management Register (PMR)
  385. Interrupt Register for Endpoint 0, 1, 2, and 3 (IIR)
  386. Interrupt Register for OUT Endpoint 1 and 2 (OIR)
  387. Interrupt Register for common USB interrupts (UIR)
  388. IN Interrupt Enable Register (IIE)
  389. OUT Interrupt Enable Register (OIE)
  390. Interrupt Enable Register (UIE)
  391. Frame Number Registers (FRAMEx)
  392. Indexed Registers
  393. IN Maximum Packet Size Register (INMAXP)
  394. Control Status Register for EP 0 (CSR0)
  395. Control Status Register 1 for IN EP 1, 2, and 3 (INCSR1)
  396. Control Status Register 2 for IN EP 1, 2, and 3 (INCSR2)
  397. OUT Maximum Packet Size Register EP 1 and 2 (OUTMAXP)
  398. Control Status Register 1 for OUT EP1 and EP2 (OUTSCSR1)
  399. Control Status Register 2 for OUT EP1 and EP 2 (OUTCSR2)
  400. Count 0 Register (OUTCOUNT0)
  401. Out Count 2 Register (OUTCOUNT2)
  402. Pending DMA Interrupts Register (INTR)
  403. DMA Channel x Control Register (CNTLx)
  404. DMA Channel x AHB Memory Address Register
  405. VIC Interrupt Listing
  406. Vectored Interrupts
  407. Clearing Interrupts
  408. FIQ Status Register (FIQSTATUS)
  409. Interrupt Select Register (INTSELECT)
  410. Interrupt Enable Clear Register (INTENCLEAR)
  411. Software Interrupt Register (SOFTINT)
  412. Software Interrupt Clear Register (SOFTINTCLEAR)
  413. Vector Address Register (VECTADDR)
  414. Vector Address Registers (VECTADDRx)
  415. Vector Control Registers (VECTCTRLx)
  416. Interrupt Test Output Register (ITOP)
  417. Figure 19-1. Watchdog Timer Block Diagram
  418. WDT Operation Details
  419. Counter Reset Register (RST)
  420. Current Watchdog Count Registers (COUNT[3:0])
/ 555
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