LH79524/LH79525 User’s Guide Synchronous Serial PortVersion 1.0 14-1514.2.2.5 Clock Prescale Register (CPSR)The CPSR Register specifies the division factor by which the input HCLK is internallydivided before use. The value programmed into this register is a value from 2 to 254. Thisregister defaults to zero, but is double buffered and reads back 1s after Reset. Becauseit resets to zero, it must be programmed prior to enabling the SSP.Table 14-11. CPSR RegisterBIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16FIELD ///RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RW RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO ROBIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0FIELD /// DVSRRESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RW WO WO WO WO WO WO WO WO RW RW RW RW RW RW RW ROADDR 0xFFFC6000 + 0x010Table 14-12. CPSR FieldsBITS NAME DESCRIPTION31:16 /// Reserved Reading returns 0. Write the reset value.15:8 /// Reserved Write as zero. Unpredictable behavior when read.7:0 DVSRClock Prescale Divisor To generate the bit rate and Serial Clock output(SSPCLK), the SSP uses two divisors on the generated 5.6448 MHz ClockInput (when using the recommended 11.2896 MHz crystal):• This programmable prescaler in the Clock Prescaler register Divisor field• A programmable clock rate divisor in the CTRL0 register (CTRL0:CPD)Program this field to the desired even-number eight-bit value between 2 and 254 forDVSR shown in the equation (note that bit zero is always 0, hence DVSR is alwaysan even number).SSPCLK is calculated as follows:SSPCLK = ƒCLOCK INPUT/(DVSR × (1 + CPD))
